Body effect

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The body effect refers to the influence of the substrate bias voltage on the threshold voltage of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It occurs when the source-to-bulk voltage alters the electric field in the channel, affecting carrier concentration and, consequently, the device's electrical characteristics.

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Key research themes

1. How do multisensory and sensorimotor integrations contribute to the sense of body ownership and body representation?

This research theme investigates the mechanisms by which various sensory modalities—visual, tactile, proprioceptive, thermosensory, nociceptive, interoceptive, and auditory—are integrated to produce the unified perceptual experience of ‘‘my body.’’ It explores how bodily self-consciousness arises from multisensory integration and sensorimotor correlations and how these processes are implicated in body ownership illusions and body image. Understanding these mechanisms illuminates both normal perception and clinical disturbances such as somatoparaphrenia and eating disorders, thereby highlighting both fundamental neuroscience and potential therapeutic avenues.

Over my fake body: body ownership illusions for studying the multisensory basis of own-body perception

by Mel Slater

2015, Frontiers in human neuroscience

Key finding: Demonstrates that the sense of body ownership arises from the brain's multisensory integration of spatially, temporally, and semantically congruent crossmodal stimuli, supported by Bayesian causal inference. By exploiting... Read more

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Multimodal Contributions to Body Representation

by Ana Tajadura-Jiménez

2023, Multisensory Research

Key finding: Synthesizes neuropsychological and behavioral evidence showing how multiple senses—including vision, touch, proprioception, vestibular function, and audition—converge and interact to build coherent body representations. The... Read more

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The Effect of Visual Capture Towards Subjective Embodiment Within the Full Body Illusion

by Catherine Preston

2022

Key finding: Finds that synchronous visuotactile stimulation is not always necessary for subjective embodiment; mere visual capture of congruent visuoproprioceptive information alone can induce illusory ownership over a mannequin's body... Read more

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Full body illusion is associated with widespread skin temperature reduction

by Roy Salomon

2017

Key finding: Finds that inducing full-body illusions (FBI) via synchronous visuotactile stimulation causes not only altered self-identification and self-location but also widespread decreases in skin temperature, linking multisensory... Read more

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Effects of pitch and musical sounds on body-representations when moving with sound

by Ana Tajadura-Jiménez

2023, Scientific Reports

Key finding: Shows that auditory features—such as pitch and musical richness—synchronously paired with bodily movement can modulate proprioceptive awareness, movement kinematics, and body-related feelings. Higher pitch and harmonic... Read more

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2. How does body ownership modulation impact physiological and social behavioral processes?

This theme focuses on the downstream consequences of experimentally manipulated body ownership illusions on physiological states and social cognition. It examines how altered body representation affects autonomic responses like skin temperature and heart rate, pain threshold modulation, and social space regulation. Understanding these effects elucidates how body self-perception is intrinsically tied to homeostatic regulation and social behavior, with implications for interventions in clinical populations with body representation disturbances.

Full body illusion is associated with widespread skin temperature reduction

by Roy Salomon

2017

Key finding: Demonstrates that the full-body illusion induces not only subjective changes in self-identification but also systemic physiological changes, such as skin temperature reductions, suggesting a link between altered body... Read more

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The body fades away: investigating the effects of transparency of an embodied virtual body on pain threshold and body ownership

by Matteo Martini

2016

Key finding: Shows that increasing transparency of a virtual embodied body weakens the illusion of body ownership and does not increase pain threshold; intriguingly, semi-transparent bodies with stronger ownership illusions correlate with... Read more

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Invisible body illusion modulates interpersonal space

by Giuseppe Di Pellegrino

2022, Scientific reports

Key finding: Finds that the illusion of owning an invisible body selectively contracts interpersonal space (IPS) boundaries without affecting peripersonal space (PPS). This dissociation implies that conscious visual representation of... Read more

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Body weight distortions in an auditory-driven body illusion in subclinical and clinical eating disorders

by Ana Tajadura-Jiménez

2023, Scientific Reports

Key finding: Reveals that individuals with high symptomatology of eating disorders (ED) and Anorexia Nervosa show different patterns of auditory-driven body size illusions compared to healthy controls, with reduced susceptibility to... Read more

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Editorial: Body Representation and Interoceptive Awareness: Cognitive, Affective, and Social Implications

by Luigi Trojano

2025, Frontiers in Psychology

Key finding: Reviews current advances linking body representation to interoceptive sensibility, highlighting contributions to affective and social domains. Emphasizes contributions showing that disturbances in body ownership are... Read more

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3. What are the conceptual and phenomenological underpinnings of bodily self-awareness and body representation distortions in healthy and pathological conditions?

This theme addresses the philosophical, phenomenological, and conceptual aspects of how bodily self-awareness arises and how body representation distortions manifest in both healthy cognition and pathological states. It explores debates on whether bodily ownership is a direct phenomenal experience or cognitively inferred, the mereological structure of the body, and distortions in spatial and metric body representations. Insights here inform the interpretation of experimental findings and guide theoretical frameworks bridging neuroscience, philosophy, and clinical observations.

What Phenomenal Contrast for Bodily Ownership

by Frederique de Vignemont

2021, Journal of the APA

Key finding: Argues that bodily ownership is not directly represented as a phenomenal property ('my-ness') in perception but consists instead in affective awareness of the body's unique significance for the self, rooted in survival. This... Read more

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Body mereology

by Frederique de Vignemont

2017

Key finding: Proposes a conceptual analysis differentiating somatosensory and motor mereologies of the body, focusing on how body parts relate to the whole body in experience and action. It identifies that bodily experience is usually... Read more

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Distorted body representations in healthy cognition

by Matthew R Longo

2016

Key finding: Synthesizes empirical evidence showing that even healthy adults possess systematic distortions in body size and position perception, underlying tactile distance and position sense, challenging assumptions of infallible bodily... Read more

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Plasticity and Awareness of Bodily Distortion

by mariella pazzaglia

2021, Neural Plasticity

Key finding: Examines multiple sources of bodily awareness—visual, innate organizational, and sensorimotor—and their respective contributions to body representation distortions. The review integrates evidence supporting that body... Read more

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Sensual Construction of Body and Biography. Suggestions to Mutually Improve Deficient but Widespread Body Concepts and Biographical Research

by Wolfram Fischer

2023, Qualitative Sociology Review

Key finding: Combines phenomenological and interactionist perspectives to argue for an integral concept of the body as lived experience ('lived body') inseparable from biography. It critiques Cartesian dualisms and advocates incorporating... Read more

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All papers in Body effect

Low Power Low Voltage Bulk Driven Balanced OTA

by Sapna Singh

2024, International Journal of VLSI Design & Communication Systems

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog... more

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Low Power Low Voltage Bulk Driven Balanced OTA

by Sapna Singh

2023, International Journal of VLSI Design & Communication Systems

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Low Power Low Voltage Bulk Driven Balanced OTA

by Sapna Singh

2023, International Journal of VLSI Design & Communication Systems

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Low Power Low Voltage Bulk Driven Balanced OTA

by Sapna Singh

2023, International Journal of VLSI Design & Communication Systems

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Role of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static and switching conditions of operation

by Nebi Caka

2023

The aim of this paper is to show the influence of the threshold voltage and transconductance parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static and switching conditions of operation, as well as... more

Fig. 1 NMOS inverter configuration with depletion type NMOS- load. 1 Introduction Key words: NMOS inverter, NMOS transistor, VTC characteristics, threshold voltage, critical voltages, nois« margins, NMOS transconductance parameter, propagation delay times.

Using drain currents of NMOS transistors in NMOS inverter depending on the input voltage levels, respectively output voltage levels, and the necessary conditions to determine the critical values can be derived expressions for the critical voltage values at the input and output of NMOS inverter, as: The values of output critical voltage Vo, are found using the numerical interaction between expressions (1) and (3), while the input critical voltage values Vi, and V;;; are found using the numerical interaction between expressions of the output voltage and the expressions for the critical values of voltage at the input. Interaction methods enable convergence of voltage critical values to the correct values. Also, static power dissipation which appears to output in low state (Vo,) depends on parameters of NMOS transistor as load [12].

Fig. 2 The NMOS-inverter with equivalent lumped capacitive load. The performance of NMOS inverter during switching conditions evaluate by propagation delays of output voltage related by input voltage. Propagation delay times are dependent on the physical and electrical parameters of the NMOS transis calculate propagation delay times will be used the NMOS inverter with an equivalent lumped linear capaci ground equivalent lumped capacitance will be called the load capacitance, which is the sum of parasitic ors which construct the NMOS inverter. To ance, connected between the output node and (C,; capacitance) shown in Fig. 2. The capaci ance components that appear in NMOS inverter.

The propagation delay time of the output voltage during the transition from high-to-low level tpy,, when the input voltage switches from low-to-high level (with negligible rise time), calculate based in Propagation delay times during transition output voltage from low-to-high level tp_y, when input voltage have transition from high-to-low level (when the fall time is negligible), calculate according to the case when the driver transistor driver goes into cut-off and load transistor goes into saturation mode of operation. After application of derivation procedure for calculation propagation delay tppy, using load drain current and capacitive current during charge up, the propagation delay time for low-to-high output transition can be expressed as,

Fig. 3 The dependence of the output voltage critical value (Vo;), aS a function of the NMOS-load threshold voltage (Vio), when Vio,~= 0.5 V. Fig. 4 The dependence of the output voltage critical value (Vo,), as a function of the NMOS-driver threshold voltage (Vio.2), when Vio;= - 0.3 V. Fig. 4 The dependence of the output voltage critical value (Vo,), as a function of the NMOS-driver threshold voltage (Vio), when V,9;= - 0.3 V.

The presented results from Fig. 6 to Fig. 11 show that for higher absolute values of the NMOS-load transistor threshold voltage, as well as the higher value of the NMOS-driver transistor threshold voltage, the input critical voltage values (V;; and Vj) will have higher values, while for higher values of the NMOS transistors transconductance parameters ratio, the input critical voltage values will be lower, with more sensitivity in the low values band of the NMOS transconductance parameters ratio. NMQOS_inverter noice maroine far honth lagcic valtace

In Fig. 15, Fig. 16 and Fig. 17 is shown the influence of the NMOS transistor threshold voltage values and the NMOS transistors transconductance parameters ratio in VTC characteristic shape. From presented characteristics show that for lower absolute values of NMOS-load transistor threshold voltage, and for lower values of NMOS-driver ransistor threshold voltage, the VTC characteristic shift to the left, compared to the higher values and he slope of the VTC characteristic remains almost he same. While the value of NMOS transistors ransconductance parameter ratio increases, the slope of the VTC characteristic rise and shows better switchine nerformances.

Fig. 16 The VTC characteristic forms of NMOS inverter for some parametric values of the NMOS- Fig. 15 The VTC characteristic forms of NMOS inverter for some parametric values of the NMOS- load transistor threshold voltage, when: Vio, q = 0.5 V,k,=4, L=0.18 um, W= 1 wmand Vpp = 2.5 V.

Fig. 17 The VTC characteristic forms of NMOS inverter for some parametric values of NMOS transistors transconductance parameters ratio (k, = k Vk) when: Vio = 0.5 V, Viol =— 0.5 V, L=0.18 um, W= 1 um and Vpp = 2.5V.

Fig. 21 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-load transistor transconductance parameters (ky < kin < ky, or ky = 2k = 6ki;), when Vio. = - 0.4 V, Vop = 2.5 V and C,; = 12 pF. Fig. 20 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-load transistor transconductance parameters (ki < ki < ky, or ky = 2k = 6ki;), when Vio. =- 0.5 V, Vpp = 2.5 V and C; = 12 pF.

Fig. 22 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-driver transistor transconductance parameters (ky < ka < kw, or kag = 2k = 10kq1), when Vio; = - 0.5 V, Vpp = 2.5 V and C, = 12 pF. Impact of Vio voltage of NMOS-driver transistor is significantly smaller in delay time tpy., compared with the impact the threshold voltage V,) of NMOS- load transistor in time delay tppy. Impact on the propagation delay time values will have also and source voltage values Vpp and equivalent capacitive load C, connected to the output of inverter (fan-out parameter).

Tab. 1 The operating regions and the voltage levels of the driver and load transistors at critical voltage values in NMOS inverter. NMOS transistors are constructed on the same substrate, therefore in NMOS transistor which acts as the load, the body effect must be taken in consideration [6, 7, 8, 9, 10, 11, 13]. Critical voltage values are determined using combinations of operation regions (operation modes) of NMOS-driver transistor and NMOS-load transistor, depending on the level of the output voltage values relative to the voltage values at the input of NMOS driver transistor (enhancement type NMOS). In Tab. 1 are shown the operating regions and the voltage levels of NMOS transistors in NMOS inverter for critical voltage values at the input of driver transistor.

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design

by Nebi Caka

2023

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo-NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

Fig. 1 The physical structure of an enhancement-type MOSFET (NMOS) in perspective view.

The pseudo-NMOS _ inverter contains two interconnected MOSFET transistors: one NMOS transistor (Qy) which works as driver and one PMOS-transistor (Qp) which works as an active load. The pseudo-NMOS inverter is shown in Fig. 2.

Fig. 3 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 1 V. Variation of the active load current (ipp) and the driver current (ipy) as function of output voltage (vo) for various values of the driver threshold voltage Qn), when the input voltage will have value of Vpp Vin = Vop, Vop = 3.3 V) and V ipo = — 0.4 V are represented in Fig. 3, Fig. 4, Fig. 5 and Fig. 6. During hese analyses the dimensions of NMOS and PMOS ransistors will be the same, while the ratio of the ransconductance process parameter (or device ransconductance parameter) will be kp = 4.

Fig. 4 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 0.7 V.

Fig. 5 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.5V.

Fig. 6 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.2V.

Fig. 7 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the active load threshold voltage is Vipp =— 1 V. Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) for various values of active load threshold voltage (Vino), where the input voltage and driver threshold voltage will be held at constant values (Vi, = Vpp, Vino = 0.4 V) are represented in Fig. 7, Fig. 8, Fig. 9, Fig. 10.

Fig. 9 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vig =— 0.5 V. Fig. 8 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Ving =— 0.7 V.

Fig. 10 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vino =— 0.2 V. Based on accrued resultants for Fig. 7 to Fig. 10 it can be concluded that: the static current J,,.; when the output is at the low logic level, it depends on the values of the load threshold voltage, and results on he lower values for higher values of active load hreshold voltage, and also for higher values of load hreshold voltage the value at low-output state will be ower. Also in this case the values of static current Isat) and output voltage (Voz) will be disadvantages of pseudo-NMOS invertors for low-output state, which will have impact in the noise margin for low evel (NM,) and static power dissipation Pp as in Fig. 11.

The active load threshold voltage (PMOS) will have impact in propagation delays during the low to high transition (tpry). For two different values of the active load threshold voltage the low to high transition is represented in Fig. 13. Fig. 13 Time response of output voltage on input voltage when the active load threshold voltage

Fig. 12 The pseudo-NMOS inverter with capacitive load C, = 0.5 pF. The values of threshold voltage which characterize the driver transistor (NMOS) and active load transistor (PMOS) will have influence on propagation delays in pseudo-NMOS invertors. For the examine time delays it will be used a pseudo- NMOS inverter which drives a capacitive load C; of 0.5 pF as in Fig 12.

Fig. 14 Time response of output voltage for two periods of input voltage when the active load threshold voltage (PMOS) has two different values and the driver threshold voltage (NMOS) holds fixed value of Vin = 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vino = — 0.3 V, the V(VOUT2) curve corresponds to the output voltage when V9 =— 0.7 V. In Fig. 14 there are represented the shapes of output voltages for two periods of inputs voltages when the active load threshold voltage has two different values.

Fig. 15 Time response of output voltage on input voltage when the driver threshold voltage (NMOS) has two different values, and the active load threshold voltage (PMOS) holds fixed value of Vipo = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vi. = 0.7V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V. during high to low transition at output voltage (¢tpyz). In Fig. 15 it is shown the impact of the driver threshold voltage in propagation delays (tex) when two different values of driver threshold voltage are considered as parametric value.

Fig. 16 Time response of output voltage for two periods of input voltage when the driver threshold voltage (NMOS) has two different values and the active load threshold voltage (PMOS) holds fixed value of Ving = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vio = 0.7 V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V.

Fig. 17 The waveforms of input and output voltages for two different values of capacitive load C;. The first case is when the capacitive load has value of C; = 0.5 pF, and second case is when load has value of C;, = 1 pF. The driver threshold voltage has two different values of 0.6V and 0.2V, whereas the active load threshold voltage has fixed value of — 0.7V.

Fig.18. Varation of the driver and active load current (Ion, Ipp) on output voltage (V,), when the input driver voltage is high (Vi, = Vpp) and the device transconductance parameters ratio has four parametric values: 4, 8, 12 and 16. The breakpoints between load curve (/p,) and driver current (/p,) will give the level values of Vor. The shape of the driver and active load currents, level value of static current and level value of low output state for some different values of device parameters ratio (kr) are shown in Fig. 18.

Fig.19 Input-output voltage transfer characteristic (VTC) of the pseudo-NMOS inverter, when the device transconductance parameter ratio has values of kr = 4, 8, 12 and 16. The variation of the VTC characteristic on kp as parametric values is shown in Fig. 19.

Fig. 20 Time response of output voltage on input voltage when the devices transconductance ratio has for different values of kp = 4, 8, 12, and 16.

Fig. 21 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Vi» = 0.7 V and active load threshold voltage is Ving = — 0.4 V. During the design phase of pseudo-NMOS logic circuits, designers must take into consideration the values of the threshold voltage of transistors which contain that logic gate. Firstly, it will begin with the VTC (voltage transfer characteristic) of pseudo- NMOS invertors and show its shape for the some different values of the driver threshold voltage where the load threshold voltage has same values as in Fig. 21 and Fig 22.

Fig. 22 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Ving = 0.2 V and active load threshold voltage is Vipgp =—0.4 V.

Fig. 23 NAND pseudo-NMOS gates with 4-inputs. In the static work regime, the values of driver threshold voltages will have impact on the value Vo,

Fig. 25 Shape of VTC-NAND gates for different number inputs (fan-in) when Vino = 0.2V. Fig. 24 Shape of VTC-NAND gates for different number inputs (fan-in) when V;,9= 0.7 V. Shape and slope of characteristics from Fig. 24 and Fig. 25 show that in the NAND gate fan-in has significant role and for higher values of number inputs (fan-in) there will be lower slope of VTC and higher values for low output state. The higher values of fan-in will result in higher values of propagation delays.

of NAND structure. The VTC-NAND shapes and values of Vo, for two different values of driver threshold voltage when fan-in has four different values are represented in Fig. 24 and Fig. 15.

Fig. 26 NOR pseudo-NMOS gates with 4-inputs.

Fig. 28 Shape of VTC NAND gates for different number inputs (fan-in) when Ving = 0.2V. Fig. 27 Shape of VTC NOR gate for different number inputs (fan-in) when V;,. = 0.7 V.

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Low Power Low Voltage Bulk Driven Balanced OTA

by Neha Gupta

2022, International Journal of VLSI Design & Communication Systems

International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011

Figure 2. Voltage Gain of Bulk Driven Balanced OTA applied to the inputs. No dc bias potential is applied to bulk terminals. The bias voltage is applied to gate terminals to bring transistor in saturation region. The output was taken between single end and ground terminal.

Figure 3. Voltage Phase of Bulk Driven Balanced OTA

It is specified on the amplifier’s data sheet in units of V/us. It implies that if the input signal applied to an amplifier circuit is of the nature that demands an output response faster than the specified value of SR, the operational amplifier will not comply. The settling time of an amplifier is very important parameter as it defines the speed at which amplifier can be sampled. The slew rate is defined as the ratio of the maximum output current to the load capacitance as shown below: 4.2 Step Response

Figure 6. Effect of Variation of Temperature on Frequency response The frequency response is shown in Figure 6. at different temperatures. The temperature is varie from -20° to 70 ° and corresponding change in gain is from 11.28dB to 12.43dB. The gain wil decrease with temperature because transconductance of opamp will decrease with temperature The decrement in transconductance is due to decrement in mobility.

Figure 7. Output Voltage Swing of Bulk Driven Balanced OTA We get the output swing (peak to peak) 550mV. In this we can apply an input signal of swing 400mV for which the output signal swing is not distorted. Simulation result is shown Figure 7.

Average power consumed at 0.9 V supply is 3.9uW. Power consumption at different power supplies are shown in Figure 8. Figure 8. Power measurements with different supply voltages (Vdd)

Figure 9(a). Input referred noise The input referred noise is 400nV/v Hz and output referred noise is 800 nV/VHz. The simulation: for noise analysis are shown in Figure 9(a) and 9(b).

International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011 Prepared circuit of amplifier is simulated at Tanner EDA T-SPICE tool at 130nm technology. The amplifier is to be powered from a 0.9 volts power supply. All values have been measured at load capacitance of | pF. The constant current source I, is 20HA.

Figure 10. Measured DC OTA responses at different common mode input voltage The output voltage is measured at different differential input (VVdiff) ranging from -0.5V to 0.9 V .This simulation is done at various common mode voltages(Vcm) ranging from 0 to 0.5V. The simulation is shown in Figure 10.

Figure 11. Output Voltage is plotted against dc sweep of input voltages Also output voltage is plotted at differential input ranging from 0 to 900mV in Figure 11. In this graph we can see that output is linearly following the input over a range of input voltage from 200 to 800mV. The linear range is 600mV.

Table 1 Simulated Results of Bulk Driven Balanced OTA

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Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

by priscilla whitin

2022, International Journal of Engineering & Technology

In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected... more

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New 1.5-V CMOS second generation current conveyor based on wide range transconductor

by Ahmed Soliman

2022, Analog Integrated Circuits and Signal Processing

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII +). The proposed CCII + uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel... more

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Role of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static and switching conditions of operation

by Myzafere Limani

2022

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS invertors

by Myzafere Limani

2022, WSEAS Transactions on …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS invertors

by Milaim Zabeli

2022, WSEAS Transactions on …

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The impact of MOSFET's physical parameters on its threshold voltage

by Milaim Zabeli

2022, Proceedings of the 6th …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold... more

Key words: MOSFET parameters, threshold voltage, body effect, enhancement-type NMOS, doped density, short: channel, narrow-channel. Fig.1 The physical structure of an n-channel enhancement-type MOSFET: (a) perspective view; (b) cross-section. Abstract: The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold voltage. The MOSFET threshold voltage value will have influence in the dynamic and static work regime (mode) of device. Based on the results obtained we can further see impact of each single physical parameter on the total value of threshold voltage. Moreover we can see which of these parameters will have significant and small impact on the threshold voltage. Hence, considering we can adjust the values of MOSFET physical parameters to reach the accepted threshold voltage.

From Fig.2 and Fig.3, based on acquired values we can see influence of ¢,,, N, and N,, in values of threshold voltage. For larger value of each parameter: tox, or Ny the value of threshold voltage will increase.

Fig.5 (a) Simplified geometry of the MOSFET channel region, with gate-induced bulk depletion region and the pn-junction depletion regions. (b) Close-up view of the drain diffusion edge. -Xas, Xap Tepresent the depth of depletion regions at source and drain as results of pn junction, respectively.

Fig.7 The dependence of the AVio on Np (source and drain doping density), when Na=10'°cm”, L=1ym, tox=20nm, xj=lum and Vps=0V.

Fig.6 The dependence of the AV; on the length Z for parametric values of depth x;, when N, = 10'° cm”, Np = 10'* cm”, t,, = 20 nm and Vps = OV.

The voltage term AV, as results of narrow-effects if shapes of the depletion region edges are modeled by quarter-circular arcs can be found as [2]:

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An Innovative Approach of High Performance CMOS Based Current Conveyor-II for ASP Applications

by Ayushi chaurasia

2022

The main purpose of the paper is to present a CMOS current conveyor circuit which is best suited for the implementation of lowvoltage, low-power and high bandwidth circuits. To achieve the bandwidth of current transfer function the... more

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Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

by Priscilla Whitin

2022, International Journal of Engineering & Technology

The circuit consists of two pumping clocks @land@2, which are anti-phase and have voltage amplitude of V@. The diodes are re- placed by MOS switches. This circuit consists of capacitor stages connected by diodes and coupled in parallel by two non- overlapping clocks. The diode-connected NMOS transistors are used instead of p-n junction diodes for developing the design in standard CMOS process. Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

To reduce the disadvantages of statics charge pump by using dy- namic charge pump.

An advanced version of Dickson charge pump it will increases the pumping gain. This type of charge pump made up of MOS switches and also capacitors. MOS switches properly ON/OFF during pumping at each stage. This type of charge pump produces forward voltage drop at each stage of pumping. In this construc- tion MS2 switch can never ever switched off totally because it can able to do reverse charge sharing between two nodes may it have reduce the leakage and also increasing the pumping gain automat- ically. Table 2: Analysis of Voltage Static charge pump

Minor changes —of CTS charge pump structure which combines the partially changes-CTS charge pump with a simplified cross- coupled output stage. A MOS switch when is completely on can pass charge from its drain to its source similar to a forward biased diode. It has the advantage that almost no voltage drop occurs between its drain and source terminal.

Fig. 6: Pumping Efficiency for each charge pump

Fig. 11: MTCMOS Charge Pump design by using Power Gating The designing of this charge pump are implemented in TANNER EDA.

Fig. 12: MTCMOS Charge Pump design by using Power Gating

Table 1: Analysis of voltage on Dickson Charge pump 2.2. Implementation of Static CTS’s in Charge Pump

2.3. Implementation of dynamic CTS’s in charge pump

Table 3: Voltage analysis of voltage dynamic charge pump The dynamic charge pump made-up off MOS switches .The work- ing principle everything like static charge pump .These type of charge pump provide low output power because of body effect, so that the NMOS transistor is connected output side.

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Fast, flexible, cycle-accurate energy estimation

by Michael Hsiao

2022, Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01

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An Innovative Approach of High Performance CMOS Based Current Conveyor-II for ASP Applications

by Dr. Rajinder Tiwari

2022

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A New Walsh Hadamard Transform Architecture Using Current Mode Circuit

by Swagata Bhattacharya

2022, 2014 IEEE Computer Society Annual Symposium on VLSI

With the reduction of supply voltage motivated by power reduction, the signal to noise ratio of digital signals has reduced. Alternately, signal can be represented as current while the supply voltage still remaining small. This gives rise... more

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The impact of MOSFET's physical parameters on its threshold voltage

by Qamil Kabashi

2021

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The threshold voltage of MOSFET and its influence on digital circuits

by Qamil Kabashi

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS inverters

by Qamil Kabashi

2021

Influence of the length channel LZ, the depth x; of drain (source) regions and drain-to-source voltage (Vps) on the voltage term AVjo, are shown in Fig.7, Fig.8.

Fig.6 Simplified geometry of the MOSFET channel region. Close-up view of the drain diffusion edge.

“ig.10 The logic “1” transfer with an NMOS. The MOS transistors in pass- transistor logic circuits used to transfer logic state between input and output nodes. During logic “1” transfer and “0” transfer the threshold voltage will have impact on level of output voltage and delay times. In Fig.10 is illustrated the logic “1” transfer with an NMOS.

Fig.13 The reduction of high output voltage level by threshold voltage (“poor 1”), when Vi9=1V. Fig.12 The reduction of high output voltage level by threshold voltage (“poor 1”), when Vy=0.6V.

Fig.11 The reduction of high output voltage level (Von) by threshold voltage (“poor 1”), when Vg=0.2V.

Fg. 14 Waveform of output voltage V, for logic “0” transfer with one pass-transistor, when V)=0.2V.

Fg. 15 Waveform of output voltage V, for logic “( transfer with one pass-transistor, when V,)=0.6V.

Fig. 18 Three identical pass-transistors connected in series. Now consider the following case in which will have three identical pass-transistors connected in series (in cascades) as in Fig. 18.

Fig. 19 Waveforms of outputs voltages when three pass-transistors connected in series, when V{9=0.6V.

Fig. 20 The logic “1” transfers when one pass- transistor is driving another pass-transistor (node voltages during the “1” transfer).

Fig.21 Waveform of outputs voltages V, for logic “1” transfer, when each pass-transistor (NMOS) is driving another pass-transistor (NMOS) and Vig = 0.6V.

The threshold voltage will have influence on critical voltages values which characterize MOS inverters and voltage transfer characteristic. The impact of V; on critical voltages values for a symmetric CMOS inverters are represented in below diagrams (for supply voltage Vpp=3.3V) Fig. 22, Fig. 23, Fig. 24 and Fig. 25.

Fig. 23 Variation of Viy (minimum input voltage which can be interpreted as logic “1”) as function of the threshold voltage V;. In symmetric case on CMOS inverters the noise margins for two levels are equal NM; =NMy.

Fig. 25 Variation of propagation delay tp as function of the threshold voltage V; 3.3 Influence of threshold voltage on critical voltage values and delay times in pseudo- NMOS inverters

Fig. 28 Variation the Vin of pseudo-NMOS inverter as function of the threshold voltage Fig. 27 Variation of the Vj, of pseudo-NMOS inverter as function of the threshold voltage V,.

Fig. 26 Variation of the threshold voltage of pseudo- NMOS inverter (Vm) as function of the threshold voltage V,..

Fig. 29 Variation of the Vo, of pseudo-NMOS inverter as function of the threshold voltage V,.

Fig. 32 Variation the les of pseudo-NMOS inverter as function of the threshold voltage

Fig. 1 The physical structure of an n-channel enhancement-type MOSFET in perspective view. Key words: Threshold Voltage, MOSFET Parameters, Enhancement-Type NMOS, Impurities, Doped Density, Short-Channel, Narrow-Channel, Voltage Level, Propagation Delay, Critical Values. The value of the gate-to-source voltage Vas needed to create (induced) the conducting channel (to cause surface inversion) is called the threshold voltage (Vi, or V;). The value of the threshold voltage is dependent from some physical parameters which characterize the MOSFET structure such as: the gate material, the thickness of oxide layer ¢,,, substrate doping concentrations (density) N4, oxide—interface fixed charge concentrations (density) N,,, channel length L, channel width W and the bias voltage Voz [1, 2, 5]. Abstract: The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits that contain the MOSFET transistors. The results obtained emphasize the impact of each single physical parameter on the total value of the threshold voltage. By adjusting the values of MOSFET physical parameters the accepted threshold voltage can be achieved. Since the threshold voltage will have influence on critical voltage values which characterise MOS inverters and delay times during transfer logic states between stages, it must be taken into consideration during design phase of logic gates that contain the MOSFET transistors. 2 The threshold voltage on MOSFET- transistors 2.1 The threshold voltage of NMOS- transistors with long-channel

Fig. 3 The dependence of the threshold voltage Vig on thickness of oxide layer t,, for parametric values of substrate doping density Ny, when N,, = 2*10'°cm?.

Fig.5 shows the dependence of the threshold voltage Vo on extra p-type impurities which is added into the channel region.

Fig.7 The dependence of the AViy on the length ZL for parametric values of depth x, when Ny = 10'° cm”, Np = 10" cm®, t,, = 20 nm and Vps = OV.

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Design Of Two Stage CMOS Operational Amplifier in 180nm Technology With Low Power and High CMRR

by deep mukherjee

2021

In this paper a CMOS two stage operational amplifier has been presented which operates at 2.5 V power supply at 0.18 micron (i.e., 180 nm) technology and whose input is depended on Bias Current. The supply voltage has been scaled down to... more

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The threshold voltage of MOSFET and its influence on digital circuits

by Myzafere Limani

2021, Proceedings of the 7th WSEAS …

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The impact of MOSFET's physical parameters on its threshold voltage

by Myzafere Limani

2021, Proceedings of the 6th …

Fig.6 The dependence of the AV, on the length L for parametric values of depth x;, when N, = 10'° cm”, Np = 10'* cm”, t,, = 20 nm and Vps = OV.

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The impact of MOSFET’s physical parameters on its threshold voltage

by Myzafere Limani

2021

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The threshold voltage of MOSFET and its influence on digital circuits

by Myzafere Limani

2021

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The impact of MOSFET's physical parameters on its threshold voltage

by Milaim Zabeli

2021, Proceedings of the 6th …

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The impact of MOSFET’s physical parameters on its threshold voltage

by Milaim Zabeli

2021

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS inverters

by Milaim Zabeli

2021

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CMOS differential current conveyors and application for analog VLSI

by Hassan Elwan

2021, Analog Integrated Circuits and Signal Processing

Novel differential current conveyor building blocks are defined. CMOS realizations of these blocks are then given. One of the proposed conveyor circuits is seen to be insensitive to the threshold voltage variation due to the body effect.... more

The MOS realization of the DCC is shown in Fig. 1(b). All transistors are assumed to be operat- ing in the saturation region with the sources connected to their substrates. The Y terminal voltage is applied to

Fig. 1a. The differential current conveyor.

Fig. 2a. The modified differential current conveyor. Fig. 2b. The MDCC circuit realization. which are operating in the ohmic region [10]. The configuration shown cancels both the even and the odd nonlinearities as discussed next.

Fig. 3a. PSPICE simulation of the voltage conveying property of the differential current conveyor.

Fig. 3b, PSPICE simulation of the differential current conveying property of the modified differential current conveyor.

Fig. 4b. A four quadrant multiplier using the MDCC. Fig. 4a. A four quadrant multiplier using the DCC. mode using op-amps, they usually suffer from the fi- nite gain-bandwidth product of the operational ampli- fiers used which limits the frequency range. The circuit shown in Fig. 5(a) represents a mixed mode second or- der bandpass filter based on the DCC. Transistors Mj and Mj. (i = 1,2) are operating in the ohmic region with their nonlinearities canceled out as shown in the previous section. The input to this filter section is a voltage while the output is a current and the transfer function is given by:

Fig. 7(b) shows the highpass and lowpass current re- sponses of this filter with Cl = 0.1nf, C2 = 0.05nf, K1 = K2=K3=30uA/V” and Vz, = —2V, Vz,, = —5V fori = 1, 2, 3. Finally a universal current mode biquad ts shown in Fig. 7(a). The lowpass, bandpass and highpass current transfer functions are given respectively by:

Fig. 4c. PSPICE simulation of the multiplier shown in Fig. 4(b).

Fig. 4d. Weighted sum multiplier circuit.

Fig. 5a. A mixed mode second order band-pass filter.

Fig. 5b. The band-pass frequency response of the filter shown in Fig. 5(a).

Fig. 6a. A current mode low pass filter using MDCC.

Fig. 6b. The frequency response of the low-pass current mode filter shown in Fig. 6(a).

Fig. 7a. A universal current mode filter based on the MDCC.

Fig. 7b. The low-pass and high-pass frequency responses of the filter shown in Fig. 7(a).

Hassan O. Elwan was born in Cairo, Egypt in 1971. He received his B.Sc. degree with honors from the elec- tronics and communication department Cairo Univer- sity 1994. He was appointed as a T.A. in the same year and is now working to receive his M.Sc. degree. His research interests include current mode circuit design, filtering, mixed D/A systems and VLSI design and test.

Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.S. degree from Cairo University, Egypt, in 1964, and the M.S. and Ph.D. degrees from the University of Pittsburgh, PA., U.S.A. in 1967 and 1970, respectively, all in electrical engineering.

Table 1. Aspect ratios for the DCC. Since 1; = J, by the current mirroring action of the transistors M3 and M4 therefore the voltage offset is given by: from the above equations AV is obtained as:

Table 2. Aspect ratios for the MDCC. Thus the cells can be used as a four quadrant mul- tiplier/transconductance. Fig. 4(c) represents the mul- tiplier output current when the voltage V1 is scanned for different values of the differential gate voltage. To realize a multiplier with a high impedance the cell of

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CMOS differential current conveyors and applications for analog VLSI

by Hassan Elwan

2021, Analog Integrated Circuits and Signal Processing

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Collapsing the CMOS transistor chain to an effective single equivalent transistor

by Spiridon Nikolaidis

2021, IEE Proceedings - Circuits, Devices and Systems

A method for collapsing the transistor chain of CMOS gates to a single equivalent transistor is introduced. The width of the equivalent transistor is calculated taking into account the operating conditions of each transistor in the... more

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A CMOS charge pump for low voltage operation

by Yiannis Moisiadis

2021, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For... more

Figure 1: The Dickson charge pump circuit with NMOS The charge pump circuit reported by Dickson has been widely used, for generating high voltages [1], [2]. The specific circuit makes use of capacitors, which are interconnected by diodes and coupled in parallel with two non-overlapping clocks. The diodes of the Dickson circuit can be replaced by NMOS as illustrated in fig. 1, resulting in a more practical implementation [1], [3], [4].

Figure 2: The NCP-2 charge pump circuit In order to overcome the above-mentioned problems, the recently reported charge pump, called NCP-2, in [5], utilises the charge transfer switches (MSi transistors). Each of the MSi transistors is controlled by the pass transistors MNi and MPi as it is presented in fig. 2. In that way the charge transfer switches can be turned off completely when required, preventing the reverse charge flow. Also they can be turned on more effectively by the high voltage generated in the next stage. More complicated schemes have been applied to increase the voltage gain, such as floating PMOS with bootstrapped gates [6], four phase clocking [7], charge transfer switches in combination with pumping the output stage with clock of enhanced voltage amplitude [5].

Figure 3: The proposed-1 charge pump circuit The proposed charge pump circuit is presented in fig.3. It utilizes the cross-connected NMOS, voltage doubler [8], as a pumping stage. The charge transfer from one stage to the next is accomplished by using a pair of PMOS as serial switches (MP; transistors). In order to ensure that during the operation of the charge pump, the well of the PMOS switches is always in the higher voltage between source and drain, we adopt the principle of bulk switching, using the MS; PMOS [9]. Two phase overlapping clocking is used to drive the pumping capacitors of each pumping stage. Better results can be obtained with the use of a non-overlapping clocking scheme.

The two versions of the proposed charge pump circuit, are compared with the MOS Dickson and the NCP-2 charge pump. The pumping capacitor values in all the charge pumps are 3pF. Figures 5-8 present the output voltage for different numbers of pumping capacitors and power supply voltages. The output current loading is 1.SuA in all cases. From these figures it is obvious that the proposed-1 charge pump circuit presents higher voltage gain when compared with the two other circuits, for all the power voltage supplies and for any number of capacitors. Figure 5: Simulated output voltages against the number of the pumping capacitors for VDD=2V

Figure 4: One stage of the proposed-2 charge pump circuit common node Vsub, to ensure that they are always tied in the higher voltage between source and drain.

Figure 6: Simulated output voltages against the number of the pumping capacitors for VDD=1.5V

A low-voltage, high performance charge pump circuit is presented. Each pumping stage consists of an improved version of the voltage doubler, with the cross-connected NMOS.

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The threshold voltage of MOSFET and its influence on digital circuits

by Myzafere Limani

2021, Proceedings of the 7th Wseas International Conference on Applied Computer and Applied Computational Science

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Influence of MOSFET parameters on its parasitic capacitance and their impact in digital circuits

by Myzafere Limani

2021, WSEAS Transactions on Circuits and Systems

Advanced development of technological processes influenced a wide use of MOSFET transistors in design of integrated digital circuits with high density packages (VLSI). However, in MOSFET transistors parasitic capacitances are present,... more

Fig. 2 Lumped representation of the parasitic MOSFET capacitances. Fig. 1 Cross-section view and the top view of typical n-channel MOSFET.

Fig. 3 Three-dimensional view of the n* diffusion regions within the p-type substrate. In the sidewalls 2, 3 and 4 p* regions we usually have density about 10N,. In practice the actual region shape is quite complicated and impurity concentration is not uniform.

In Fig. 4 is shown the dependence of gate capacitive effect in the so-called “worst case” conditions on area S (product between width and length channel), for parametric values of thickness of oxide layers (t,,). With the so-called “‘worst case” we understand the case when gate capacitive effect reaches its maximal value.

Fig. 6 Dependence of junction capacitance drain- body Cq and W on parametrical values of Y of drain region, for: x, = 0.4 ym, Ny =4-10'° cm®, Np =2-10"° cm®, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.

Fig. 7 Dependence of junction capacitance drain- body Ca, and W on parametrical values of Y of drain region, for x, = 0.8 ym, Ny =4-10 cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.

Fig. 8 Dependence of junction capacitance drain- body Ca and W on parametrical values of Y of drain region, for x; = lym, Na = 4:10" cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm; V; =OV and V2 =—5V.

To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, firstly we consider the depletion region thickness, which is xg. Assuming that the n-type and p-type doping densities are given by Np and Na, respectively, and that reverse bias voltage is given by V (negative), the depletion region thickness can be calculated as [3, 5]:

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The impact of MOSFET's physical parameters on its threshold voltage

by Myzafere Limani

2021, Proceedings of the 6th …

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Exercise Problems

by 鹏曾

2017

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EMIONS: RF AND TP 11.4: A i V CMOS Opamp Using Bulk-Driven MOSFETs

by achar farance

2016

IC technology trends suggest that future implementation of mixed analog-digital circuits using standard CMOS w i l l have power supplies of S1.5V [I-21. Furthermore, it is anticipated that the threshold voltages will not eignificantly... more

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Low-Voltage digitally controlled fully differential current conveyor

by ahmed soliman

2016, IEEE Transactions on Circuits and Systems I-regular Papers

Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of... more

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Novel compensated CMOS buffer

by ahmed soliman

2016, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003

VDII ~ I A new CMOS buffer is introduced. A compensation circuit is used to cancel the output voltage offset resulting from the body effect. The voltage offset cancellation is achieved over all the input range hence resulting in a highly... more

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A CMOS charge pump for low voltage operation

by Yiannis Moisiadis and

2016, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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A CMOS charge pump for low voltage operation

by Ilias Bouras

2016, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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A 21nW CMOS Operational Amplifier for Biomedical Application

by SWAPNIL SOURAV and

2015

Cadence analog & digital system design tools of UMC 90nm C M O S technology.

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LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTA

by International journal of VLSI design & Communication Systems (VLSICS) and

2015

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A 21nW CMOS Operational amplifier for Biomedical Application

by SWAPNIL SOURAV

2015

In this paper CMOS operational amplifier using a two stage has been enunciated for low power device application by using it in subthreshold region. The proposed Op amp shows high gain as well as moderate UGB using capacitor compensation... more

Fig. 1. Proposed Temperature Sensor In this section, simulation result of the proposed op amp is described. The presented Op amp has been designed in 90nm CMOS process with 500fF load capacitor and simulated in cadence analog and digital design system.

Fig. 3. AC Response of Op amp Fig. 2. Transisent Analysis of Proposed Op amp

The overall resultant power dissipation of the proposed op amp is 21 nW.

Fig. 4. AC Response at different temperature -50°C to +50 °C

Fig. 5. Monte Carlo simulation result for 10mV variation in threshold voltage in Gain

Fig. 6. Monte Carlo simulation result for 10mV variation in threshold voltage in Phase margin

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Novel Accurate Wideband CMOS Current Conveyor

by Hassan Hassan

2015, Frequenz

The CMOS realization of the proposed wideband and low input resistance CCII is shown in Fig. 2. The groups of the transistors (M1-M4), (M5 and M7), (M8 and M9), (M10 and M11), (M13 and M15) as well as (M16 and M17) are matched. Assuming that Fig. 1: The CCIl realization reported in [7]

Fig. 2: The proposed wideband and low input resistance CCI Index Terms — wideband, CMOS current conveyor, analog circuits

Fig. 4: Frequency characteristics of the open circuit voltage transfer gain between Y and X (VX/VY) for the circuit shown in Fig. 2

Fig. 5: Frequency characteristics of the short circuit current transfer gain between X and Z (IZ/IX) for the circuit shown in Fig. 2 A fair comparison can be held between the proposed CCII* and Yodprasit CCI’ reported in [7]. From Table 3, it can be observed

Fig. 7: The transient response of the circuit shown in Fig. 2 Fig. 6: Input impedance at terminal X for the circuit shown in Fig. 2

Table 2: Transistors aspect ratios of the circuit shown in Fig. 2 Also, the transient response of the closed loop circuit is simulat- ed for an input square wave at terminal Y. The input square wave has 0.4V peak to peak amplitude, 0.5 MHz fundamental frequen- cy and Ins rise time. The output at terminal X is shown in Fig. 6. It can be noticed that it represents a faithful replica of the input square wave with no overshoots or oscillations.

Table 1: Transistors aspect ratios of the circuit shown in Fig.1 set varies from 0.16uA to 7.5uA within the input current range. The average value of the short circuit current transfer gain equals 0.98211. The short circuit current transfer bandwidth exhibits a 3- dB frequency of 107 MHz (Fig. 4).The input resistance at termi- nal X at DC equals 0.82 Q (Fig. 5). The total harmonic distortion (THD) of an input sinusoid of frequency 100 KHz and amplitude 0.5V peak to peak is 0.005%. The power dissipation of the circuit equals 0.87 mW.

Table 3: Parameters of the circuits shown in Fig. 1 and Fig. 2

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0.8V bulk-driven variable gain amplifier

by George Raikos

2014

A low-voltage variable gain amplifier based on PMOS bulk-driven input stage is presented in this paper. The gain of the proposed amplifier has a linear in-dB gain dependency since it utilizes the conventional pseudo exponential... more

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0.8V bulk-driven variable gain amplifier

by George Raikos

2014

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0.8V bulk-driven variable gain amplifier

by George Raikos

2014

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New 1.5-V CMOS Current Feedback Operational Amplifier

by soliman mahmoud

2013

a novel CMOS low-voltage current feedback operational amplifier (CFOA) is presented. The proposed CFOA based on a new positive second-generation current conveyor (CCII+). The new circuit allows almost a rail-to-rail input and output... more

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