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Fig. 3 Three-dimensional view of the n* diffusion regions within the p-type substrate. In the sidewalls 2, 3 and 4 p* regions we usually have density about 10N,. In practice the actual region shape is quite complicated and impurity concentration is not uniform.

Figure 3 Three-dimensional view of the n* diffusion regions within the p-type substrate. In the sidewalls 2, 3 and 4 p* regions we usually have density about 10N,. In practice the actual region shape is quite complicated and impurity concentration is not uniform.

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Fig. 2 Lumped representation of the parasitic MOSFET capacitances. Fig. 1 Cross-section view and the top view of typical n-channel MOSFET.
Fig. 2 Lumped representation of the parasitic MOSFET capacitances. Fig. 1 Cross-section view and the top view of typical n-channel MOSFET.
To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, firstly we consider the depletion region thickness, which is xg. Assuming that the n-type and p-type doping densities are given by Np and Na, respectively, and that reverse bias voltage is given by V (negative), the depletion region thickness can be calculated as [3, 5]:
To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, firstly we consider the depletion region thickness, which is xg. Assuming that the n-type and p-type doping densities are given by Np and Na, respectively, and that reverse bias voltage is given by V (negative), the depletion region thickness can be calculated as [3, 5]:
In Fig. 4 is shown the dependence of gate capacitive effect in the so-called “worst case” conditions on area S (product between width and length channel), for parametric values of thickness of oxide layers (t,,). With the so-called “‘worst case” we understand the case when gate capacitive effect reaches its maximal value.
In Fig. 4 is shown the dependence of gate capacitive effect in the so-called “worst case” conditions on area S (product between width and length channel), for parametric values of thickness of oxide layers (t,,). With the so-called “‘worst case” we understand the case when gate capacitive effect reaches its maximal value.
Fig. 6 Dependence of junction capacitance drain- body Cq and W on parametrical values of Y of drain region, for: x, = 0.4 ym, Ny =4-10'° cm®, Np =2-10"° cm®, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.
Fig. 6 Dependence of junction capacitance drain- body Cq and W on parametrical values of Y of drain region, for: x, = 0.4 ym, Ny =4-10'° cm®, Np =2-10"° cm®, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.
Fig. 7 Dependence of junction capacitance drain- body Ca, and W on parametrical values of Y of drain region, for x, = 0.8 ym, Ny =4-10 cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.
Fig. 7 Dependence of junction capacitance drain- body Ca, and W on parametrical values of Y of drain region, for x, = 0.8 ym, Ny =4-10 cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.
Fig. 8 Dependence of junction capacitance drain- body Ca and W on parametrical values of Y of drain region, for x; = lym, Na = 4:10" cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm; V; =OV and V2 =—5V.
Fig. 8 Dependence of junction capacitance drain- body Ca and W on parametrical values of Y of drain region, for x; = lym, Na = 4:10" cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm; V; =OV and V2 =—5V.
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MOSFET parameters
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