In this paper a CMOS two stage operational amplifier has been presented which operates at 2.5 V p... more In this paper a CMOS two stage operational amplifier has been presented which operates at 2.5 V power supply at 0.18 micron (i.e., 180 nm) technology and whose input is depended on Bias Current. The supply voltage has been scaled down to reduce overall power consumption of the system. The main aim of our work is to decrease power dissipation .At large supply voltages, there is a trade-off among speed, power and gain. Performance of any circuit depends upon speed, power and gain. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 36.747dB and a -3db bandwidth of 7.33 kHz and a unity gain bandwidth of 16.54 MHz for a load of 3 pF compensation capacitor & 10 pF load Capacitor. This op-amp has a PSRR (+) of 179.3dB , Common Mode gain of -102.4 dB, with a high CMRR of 133.69 dB and an output slew rate of 12.5 v/μs. The power consumption for the op-amp is .80...
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Papers by deep mukherjee