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Figure 1: The Dickson charge pump circuit with NMOS The charge pump circuit reported by Dickson has been widely used, for generating high voltages [1], [2]. The specific circuit makes use of capacitors, which are interconnected by diodes and coupled in parallel with two non-overlapping clocks. The diodes of the Dickson circuit can be replaced by NMOS as illustrated in fig. 1, resulting in a more practical implementation [1], [3], [4].

Figure 1 The Dickson charge pump circuit with NMOS The charge pump circuit reported by Dickson has been widely used, for generating high voltages [1], [2]. The specific circuit makes use of capacitors, which are interconnected by diodes and coupled in parallel with two non-overlapping clocks. The diodes of the Dickson circuit can be replaced by NMOS as illustrated in fig. 1, resulting in a more practical implementation [1], [3], [4].

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Figure 2: The NCP-2 charge pump circuit In order to overcome the above-mentioned problems, the recently reported charge pump, called NCP-2, in [5], utilises the charge transfer switches (MSi transistors). Each of the MSi transistors is controlled by the pass transistors MNi and MPi as it is presented in fig. 2. In that way the charge transfer switches can be turned off completely when required, preventing the reverse charge flow. Also they can be turned on more effectively by the high voltage generated in the next stage. More complicated schemes have been applied to increase the voltage gain, such as floating PMOS with bootstrapped gates [6], four phase clocking [7], charge transfer switches in combination with pumping the output stage with clock of enhanced voltage amplitude [5].
Figure 2: The NCP-2 charge pump circuit In order to overcome the above-mentioned problems, the recently reported charge pump, called NCP-2, in [5], utilises the charge transfer switches (MSi transistors). Each of the MSi transistors is controlled by the pass transistors MNi and MPi as it is presented in fig. 2. In that way the charge transfer switches can be turned off completely when required, preventing the reverse charge flow. Also they can be turned on more effectively by the high voltage generated in the next stage. More complicated schemes have been applied to increase the voltage gain, such as floating PMOS with bootstrapped gates [6], four phase clocking [7], charge transfer switches in combination with pumping the output stage with clock of enhanced voltage amplitude [5].
Figure 3: The proposed-1 charge pump circuit The proposed charge pump circuit is presented in fig.3. It utilizes the cross-connected NMOS, voltage doubler [8], as a pumping stage. The charge transfer from one stage to the next is accomplished by using a pair of PMOS as serial switches (MP; transistors). In order to ensure that during the operation of the charge pump, the well of the PMOS switches is always in the higher voltage between source and drain, we adopt the principle of bulk switching, using the MS; PMOS [9]. Two phase overlapping clocking is used to drive the pumping capacitors of each pumping stage. Better results can be obtained with the use of a non-overlapping clocking scheme.
Figure 3: The proposed-1 charge pump circuit The proposed charge pump circuit is presented in fig.3. It utilizes the cross-connected NMOS, voltage doubler [8], as a pumping stage. The charge transfer from one stage to the next is accomplished by using a pair of PMOS as serial switches (MP; transistors). In order to ensure that during the operation of the charge pump, the well of the PMOS switches is always in the higher voltage between source and drain, we adopt the principle of bulk switching, using the MS; PMOS [9]. Two phase overlapping clocking is used to drive the pumping capacitors of each pumping stage. Better results can be obtained with the use of a non-overlapping clocking scheme.
The two versions of the proposed charge pump circuit, are compared with the MOS Dickson and the NCP-2 charge pump. The pumping capacitor values in all the charge pumps are 3pF. Figures 5-8 present the output voltage for different numbers of pumping capacitors and power supply voltages. The output current loading is 1.SuA in all cases. From these figures it is obvious that the proposed-1 charge pump circuit presents higher voltage gain when compared with the two other circuits, for all the power voltage supplies and for any number of capacitors. Figure 5: Simulated output voltages against the number of the pumping capacitors for VDD=2V
The two versions of the proposed charge pump circuit, are compared with the MOS Dickson and the NCP-2 charge pump. The pumping capacitor values in all the charge pumps are 3pF. Figures 5-8 present the output voltage for different numbers of pumping capacitors and power supply voltages. The output current loading is 1.SuA in all cases. From these figures it is obvious that the proposed-1 charge pump circuit presents higher voltage gain when compared with the two other circuits, for all the power voltage supplies and for any number of capacitors. Figure 5: Simulated output voltages against the number of the pumping capacitors for VDD=2V
Figure 4: One stage of the proposed-2 charge pump circuit common node Vsub, to ensure that they are always tied in the higher voltage between source and drain.
Figure 4: One stage of the proposed-2 charge pump circuit common node Vsub, to ensure that they are always tied in the higher voltage between source and drain.
Figure 6: Simulated output voltages against the number of the pumping capacitors for VDD=1.5V
Figure 6: Simulated output voltages against the number of the pumping capacitors for VDD=1.5V
A low-voltage, high performance charge pump circuit is presented. Each pumping stage consists of an improved version of the voltage doubler, with the cross-connected NMOS.
A low-voltage, high performance charge pump circuit is presented. Each pumping stage consists of an improved version of the voltage doubler, with the cross-connected NMOS.
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Low Power ElectronicsCharge PumpCharge PumpsBody effect
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