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The pseudo-NMOS _ inverter contains two interconnected MOSFET transistors: one NMOS transistor (Qy) which works as driver and one PMOS-transistor (Qp) which works as an active load. The pseudo-NMOS inverter is shown in Fig. 2.

Figure 2 The pseudo-NMOS _ inverter contains two interconnected MOSFET transistors: one NMOS transistor (Qy) which works as driver and one PMOS-transistor (Qp) which works as an active load. The pseudo-NMOS inverter is shown in Fig. 2.

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Fig. 1 The physical structure of an enhancement-type MOSFET (NMOS) in perspective view.
Fig. 1 The physical structure of an enhancement-type MOSFET (NMOS) in perspective view.
Fig. 3 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 1 V. Variation of the active load current (ipp) and the driver current (ipy) as function of output voltage (vo) for various values of the driver threshold voltage Qn), when the input voltage will have value of Vpp Vin = Vop, Vop = 3.3 V) and V ipo = — 0.4 V are represented in Fig. 3, Fig. 4, Fig. 5 and Fig. 6. During hese analyses the dimensions of NMOS and PMOS ransistors will be the same, while the ratio of the ransconductance process parameter (or device ransconductance parameter) will be kp = 4.
Fig. 3 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 1 V. Variation of the active load current (ipp) and the driver current (ipy) as function of output voltage (vo) for various values of the driver threshold voltage Qn), when the input voltage will have value of Vpp Vin = Vop, Vop = 3.3 V) and V ipo = — 0.4 V are represented in Fig. 3, Fig. 4, Fig. 5 and Fig. 6. During hese analyses the dimensions of NMOS and PMOS ransistors will be the same, while the ratio of the ransconductance process parameter (or device ransconductance parameter) will be kp = 4.
Fig. 4 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 0.7 V.
Fig. 4 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 0.7 V.
Fig. 5 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.5V.
Fig. 5 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.5V.
Fig. 6 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.2V.
Fig. 6 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.2V.
Fig. 7 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the active load threshold voltage is Vipp =— 1 V. Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) for various values of active load threshold voltage (Vino), where the input voltage and driver threshold voltage will be held at constant values (Vi, = Vpp, Vino = 0.4 V) are represented in Fig. 7, Fig. 8, Fig. 9, Fig. 10.
Fig. 7 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the active load threshold voltage is Vipp =— 1 V. Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) for various values of active load threshold voltage (Vino), where the input voltage and driver threshold voltage will be held at constant values (Vi, = Vpp, Vino = 0.4 V) are represented in Fig. 7, Fig. 8, Fig. 9, Fig. 10.
Fig. 9 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vig =— 0.5 V. Fig. 8 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Ving =— 0.7 V.
Fig. 9 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vig =— 0.5 V. Fig. 8 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Ving =— 0.7 V.
Fig. 10 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vino =— 0.2 V. Based on accrued resultants for Fig. 7 to Fig. 10 it can be concluded that: the static current J,,.; when the output is at the low logic level, it depends on the values of the load threshold voltage, and results on he lower values for higher values of active load hreshold voltage, and also for higher values of load hreshold voltage the value at low-output state will be ower. Also in this case the values of static current Isat) and output voltage (Voz) will be disadvantages of pseudo-NMOS invertors for low-output state, which will have impact in the noise margin for low evel (NM,) and static power dissipation Pp as in Fig. 11.
Fig. 10 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vino =— 0.2 V. Based on accrued resultants for Fig. 7 to Fig. 10 it can be concluded that: the static current J,,.; when the output is at the low logic level, it depends on the values of the load threshold voltage, and results on he lower values for higher values of active load hreshold voltage, and also for higher values of load hreshold voltage the value at low-output state will be ower. Also in this case the values of static current Isat) and output voltage (Voz) will be disadvantages of pseudo-NMOS invertors for low-output state, which will have impact in the noise margin for low evel (NM,) and static power dissipation Pp as in Fig. 11.
The active load threshold voltage (PMOS) will have impact in propagation delays during the low to high transition (tpry). For two different values of the active load threshold voltage the low to high transition is represented in Fig. 13. Fig. 13 Time response of output voltage on input voltage when the active load threshold voltage
The active load threshold voltage (PMOS) will have impact in propagation delays during the low to high transition (tpry). For two different values of the active load threshold voltage the low to high transition is represented in Fig. 13. Fig. 13 Time response of output voltage on input voltage when the active load threshold voltage
Fig. 12 The pseudo-NMOS inverter with capacitive load C, = 0.5 pF. The values of threshold voltage which characterize the driver transistor (NMOS) and active load transistor (PMOS) will have influence on propagation delays in pseudo-NMOS invertors. For the examine time delays it will be used a pseudo- NMOS inverter which drives a capacitive load C; of 0.5 pF as in Fig 12.
Fig. 12 The pseudo-NMOS inverter with capacitive load C, = 0.5 pF. The values of threshold voltage which characterize the driver transistor (NMOS) and active load transistor (PMOS) will have influence on propagation delays in pseudo-NMOS invertors. For the examine time delays it will be used a pseudo- NMOS inverter which drives a capacitive load C; of 0.5 pF as in Fig 12.
Fig. 14 Time response of output voltage for two periods of input voltage when the active load threshold voltage (PMOS) has two different values and the driver threshold voltage (NMOS) holds fixed value of Vin = 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vino = — 0.3 V, the V(VOUT2) curve corresponds to the output voltage when V9 =— 0.7 V. In Fig. 14 there are represented the shapes of output voltages for two periods of inputs voltages when the active load threshold voltage has two different values.
Fig. 14 Time response of output voltage for two periods of input voltage when the active load threshold voltage (PMOS) has two different values and the driver threshold voltage (NMOS) holds fixed value of Vin = 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vino = — 0.3 V, the V(VOUT2) curve corresponds to the output voltage when V9 =— 0.7 V. In Fig. 14 there are represented the shapes of output voltages for two periods of inputs voltages when the active load threshold voltage has two different values.
Fig. 15 Time response of output voltage on input voltage when the driver threshold voltage (NMOS) has two different values, and the active load threshold voltage (PMOS) holds fixed value of Vipo = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vi. = 0.7V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V. during high to low transition at output voltage (¢tpyz). In Fig. 15 it is shown the impact of the driver threshold voltage in propagation delays (tex) when two different values of driver threshold voltage are considered as parametric value.
Fig. 15 Time response of output voltage on input voltage when the driver threshold voltage (NMOS) has two different values, and the active load threshold voltage (PMOS) holds fixed value of Vipo = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vi. = 0.7V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V. during high to low transition at output voltage (¢tpyz). In Fig. 15 it is shown the impact of the driver threshold voltage in propagation delays (tex) when two different values of driver threshold voltage are considered as parametric value.
Fig. 16 Time response of output voltage for two periods of input voltage when the driver threshold voltage (NMOS) has two different values and the active load threshold voltage (PMOS) holds fixed value of Ving = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vio = 0.7 V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V.
Fig. 16 Time response of output voltage for two periods of input voltage when the driver threshold voltage (NMOS) has two different values and the active load threshold voltage (PMOS) holds fixed value of Ving = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vio = 0.7 V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V.
Fig. 17 The waveforms of input and output voltages for two different values of capacitive load C;. The first case is when the capacitive load has value of C; = 0.5 pF, and second case is when load has value of C;, = 1 pF. The driver threshold voltage has two different values of 0.6V and 0.2V, whereas the active load threshold voltage has fixed value of — 0.7V.
Fig. 17 The waveforms of input and output voltages for two different values of capacitive load C;. The first case is when the capacitive load has value of C; = 0.5 pF, and second case is when load has value of C;, = 1 pF. The driver threshold voltage has two different values of 0.6V and 0.2V, whereas the active load threshold voltage has fixed value of — 0.7V.
Fig.18. Varation of the driver and active load current (Ion, Ipp) on output voltage (V,), when the input driver voltage is high (Vi, = Vpp) and the device transconductance parameters ratio has four parametric values: 4, 8, 12 and 16. The breakpoints between load curve (/p,) and driver current (/p,) will give the level values of Vor. The shape of the driver and active load currents, level value of static current and level value of low output state for some different values of device parameters ratio (kr) are shown in Fig. 18.
Fig.18. Varation of the driver and active load current (Ion, Ipp) on output voltage (V,), when the input driver voltage is high (Vi, = Vpp) and the device transconductance parameters ratio has four parametric values: 4, 8, 12 and 16. The breakpoints between load curve (/p,) and driver current (/p,) will give the level values of Vor. The shape of the driver and active load currents, level value of static current and level value of low output state for some different values of device parameters ratio (kr) are shown in Fig. 18.
Fig.19 Input-output voltage transfer characteristic (VTC) of the pseudo-NMOS inverter, when the device transconductance parameter ratio has values of kr = 4, 8, 12 and 16. The variation of the VTC characteristic on kp as parametric values is shown in Fig. 19.
Fig.19 Input-output voltage transfer characteristic (VTC) of the pseudo-NMOS inverter, when the device transconductance parameter ratio has values of kr = 4, 8, 12 and 16. The variation of the VTC characteristic on kp as parametric values is shown in Fig. 19.
Fig. 20 Time response of output voltage on input voltage when the devices transconductance ratio has for different values of kp = 4, 8, 12, and 16.
Fig. 20 Time response of output voltage on input voltage when the devices transconductance ratio has for different values of kp = 4, 8, 12, and 16.
Fig. 21 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Vi» = 0.7 V and active load threshold voltage is Ving = — 0.4 V. During the design phase of pseudo-NMOS logic circuits, designers must take into consideration the values of the threshold voltage of transistors which contain that logic gate. Firstly, it will begin with the VTC (voltage transfer characteristic) of pseudo- NMOS invertors and show its shape for the some different values of the driver threshold voltage where the load threshold voltage has same values as in Fig. 21 and Fig 22.
Fig. 21 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Vi» = 0.7 V and active load threshold voltage is Ving = — 0.4 V. During the design phase of pseudo-NMOS logic circuits, designers must take into consideration the values of the threshold voltage of transistors which contain that logic gate. Firstly, it will begin with the VTC (voltage transfer characteristic) of pseudo- NMOS invertors and show its shape for the some different values of the driver threshold voltage where the load threshold voltage has same values as in Fig. 21 and Fig 22.
Fig. 22 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Ving = 0.2 V and active load threshold voltage is Vipgp =—0.4 V.
Fig. 22 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Ving = 0.2 V and active load threshold voltage is Vipgp =—0.4 V.
Fig. 23 NAND pseudo-NMOS gates with 4-inputs. In the static work regime, the values of driver threshold voltages will have impact on the value Vo,
Fig. 23 NAND pseudo-NMOS gates with 4-inputs. In the static work regime, the values of driver threshold voltages will have impact on the value Vo,
Fig. 25 Shape of VTC-NAND gates for different number inputs (fan-in) when Vino = 0.2V. Fig. 24 Shape of VTC-NAND gates for different number inputs (fan-in) when V;,9= 0.7 V. Shape and slope of characteristics from Fig. 24 and Fig. 25 show that in the NAND gate fan-in has significant role and for higher values of number inputs (fan-in) there will be lower slope of VTC and higher values for low output state. The higher values of fan-in will result in higher values of propagation delays.
Fig. 25 Shape of VTC-NAND gates for different number inputs (fan-in) when Vino = 0.2V. Fig. 24 Shape of VTC-NAND gates for different number inputs (fan-in) when V;,9= 0.7 V. Shape and slope of characteristics from Fig. 24 and Fig. 25 show that in the NAND gate fan-in has significant role and for higher values of number inputs (fan-in) there will be lower slope of VTC and higher values for low output state. The higher values of fan-in will result in higher values of propagation delays.
of NAND structure. The VTC-NAND shapes and values of Vo, for two different values of driver threshold voltage when fan-in has four different values are represented in Fig. 24 and Fig. 15.
of NAND structure. The VTC-NAND shapes and values of Vo, for two different values of driver threshold voltage when fan-in has four different values are represented in Fig. 24 and Fig. 15.
Fig. 26 NOR pseudo-NMOS gates with 4-inputs.
Fig. 26 NOR pseudo-NMOS gates with 4-inputs.
Fig. 28 Shape of VTC NAND gates for different number inputs (fan-in) when Ving = 0.2V. Fig. 27 Shape of VTC NOR gate for different number inputs (fan-in) when V;,. = 0.7 V.
Fig. 28 Shape of VTC NAND gates for different number inputs (fan-in) when Ving = 0.2V. Fig. 27 Shape of VTC NOR gate for different number inputs (fan-in) when V;,. = 0.7 V.
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EngineeringElectronic EngineeringLogic GateMOSFET parameters
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