Digital Logic

This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented.

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology, which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMOS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Abstract--- Image compression is an important topic in digital world. It is the art of representing the information in a compact form. We present a new design of low-power and high speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs).The architecture of DCT is based on Lo-effler method which is a fast and low complexity algorithm. The DCT optimization is based on the hardware simplification of the multipliers used to compute the DCT coefficients. Low power approaches like Canonic signed digit representation for constant coefficients and sub-expression elimination methods have been used. The 2D DCT is performed on 8x8 image matrix using two 1D DCT blocks and a transposition block. Similar to DCT, the IDCT is also implemented using the Lo-effler algorithm for IDCT. Verilog HDL is used to implement the design. ISIM of XILINX is used for the simulation of the design. X power analyzer tool of xilinx is used to obtain the detailed dynamic power report of the design. MATLAB is used as the support tool to obtain the input pixel values of the image.

The system-on-chip design methodology is a new paradigm for electrical and computer engineering education in digital logic and microelectronics. The development of a close relationship between the undergraduate course sequence in digital logic and behavioral synthesis and that in electronics and microelectronics has been problematical until now. The system design issues considered by these two historically distinct course sequences usually did not have very much in common. The Western Design Center, Inc., Mesa, AZ, USA and the Department of Electrical and Computer Engineering, Temple University, Philadelphia, PA, USA have now established the System Chip Design Center to address these issues in engineering education and the resulting system-on-chip design methodology. The traditional undergraduate sequence in digital logic consists of three courses: combinational and sequential logic with schematic capture and a register transfer language; a processor architecture and assembly langua...

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10 nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

In this investigation, a novel numerical method is proposed for materials selection. This method is based on the well known weighting factor approach while combining non-linear normalization with a modified digital logic method. The proposed mathematical functions and their applicability to the materials selection process is verified by examining two case studies in mechanical design and comparing the results with those obtained from the classical weighted property method. It is concluded that the new approach is capable of providing more reasonable selections as opposed to those obtained from the existing method.

This article looks at Propositional Logic, also called Statement Calculus, from a combinatorial and algebraic point of view, its implementation in software, and its application to digital electronics. An historical section covers the shift in viewpoint from classical logic (based on Aristotle’s syllogism) to modern symbolic logic, with the key papers (1830-1881) that drove this shift shared in the online logic sourcebook section of the references.

As a practical aid, we implement the grammar of the statement calculus in the Symbolic Logic Simulator (SLS), a program written in 28 lines of Forth, that allows computer-aided verification of any theorem in Propositional Logic (see Appendix 1 for source code). The program makes it straight-forward to explore non-obvious logical identities, and verify any propositional logic theorem or conjecture, in particular see Appendix 2 for key identities in the statement calculus (duality, algebraic, and canonical identities).

The concept of linguistic adequacy is developed iand the NAND Adequacy Theorem is proved showing that NAND can generate all logical operations. A corollary is that any digital logic circuit can be built up entirely using NAND gates, illustrated using the free Digital Works software

With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. As a general overview of fault-tolerance, we start with comparing on-going techniques for fault-tolerant design. Later, we explain the two basic terminologies of MRF i.e. Joint and Marginal Probability followed by their computation for M3 module of C432 Interrupt Controller (as our test circuit). The contribution of this paper is the derivation of circuit design rules based on the conclusions obtained by these two probability analyses.

This paper will describe the development of a prototype software toolbox that can analyze and process a Simulink block diagram model in order to produce a VHDL representation of the model. The derived VHDL model will consist of a combination of behavioural, RTL and structural definitions mapped directly from the Simulink model. This approach may enable a user to develop and simulate a digital control algorithm using Matlab and once complete, convert this to VHDL code. This would then be synthesized into digital logic hardware for implementation on devices such as FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits).

In this paper, we investigate the advantages and feasibility of motor control using very fast (in megahertz) switching in place of traditional amplifiers. We also propose integrated motioncontrol architecture based on discrete-event control approach to be implemented in digital logic at an equally high rate. A switching controller combines the current and motion feedback paths into a single loop. A model-based observer estimates the load torque. When compared to second-order controllers implemented with traditional amplifiers, the proposed design promises increased performance, better efficiency, and improved load estimation. Simple implementation makes concepts of switching control very attractive in motion-control systems like control of dc or ac servomotors. The control algorithm designed by the proposed approach can be easily implemented on field programmable gate array platforms.

In this paper we present a new hybrid transform based on the Kronecker product of Reed-Muller and Reed-Muller Haar transforms. The proposed transform shares attractive properties of both Reed-Muller transform and Reed-Muller Haar transform. An example of application of ...

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

Quantum-dot cellular automata (QCA) is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. A QCA latch is an elementary building block which can be used to build shift registers and logic devices for clocked QCA architectures. We discuss the operation of a QCA latch and a shift register and present an analysis of the types and properties of errors encountered in their operation.

AbstractÐSeveral problems in digital logic can be conveniently approached in the spectral domain. In this paper we show that the Walsh spectrum of Boolean functions can be analyzed by looking at algebraic properties of a class of Cayley graphs associated with Boolean functions. We use this idea to investigate the Walsh spectrum of certain special functions.

The Dagstuhl seminar 08371 on Fault-Tolerant Distributed Algorithms on VLSI Chips was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of futuregeneration VLSI chips. Participants from both the distributed fault-tolerant algorithms community, interested in this emerging application domain, and from the VLSI systems-on-chip and digital design community, interested in well-founded system-level approaches to fault-tolerance, ...

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18µm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

Analog to digital converter (ADC) is the crucial part of many mixed-signal ICs because it interfaces analog signals from real world with digital logic on a chip. Faults made during ADC hardly can be repaired within the digital part. Therefore, functional testing of ADC is a very important task especially during prototyping. In this paper one laboratory ADC tester is proposed. It is based on NI-6251 data acquisition card and a PC that controls the testing process using LabView software.

The resonant tunneling diode (RTD) has been widely studied because of its importance in the field of nanoelectronic science and technology and its potential applications in very high speed/functionality devices and circuits. Even though much progress has been made in this regard, additional work is needed to realize the full potential of RTD's. As research on RTD's continues, we will try in this tutorial review to provide the reader with an overall and succinct picture of where we stand in this exciting field of research and to address the following questions: What makes RTD's so attractive? To what extent can RTD's be modeled for design purposes? What are the required and achievable device properties in terms of digital logic applications? To address these issues, we review the device operational principles, various modeling approaches, and major device properties. Comparisons among the various RTD physical models and major features of RTD's, resonant interband tunneling diodes, and Esaki tunnel diodes are presented. The tutorial and analysis provided in this paper may help the reader in becoming familiar with current research efforts, as well as to examine the important aspects in further RTD developments and their circuit applications.

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes are presented. A relay with three equally sized input electrodes is demonstrated to perform various threeinput logic functions, with a delay that can be well predicted by a lumped-parameter model. Relays with differently sized input electrodes can be used to perform more complex functions. A flash-type analog-to-digital converter is presented as one example.

We demonstrate a standalone (no global clock) receiver for two-dimensional wavelength-time optical code-division multiple-access. The receiver provides the following functions: quantization (to eliminate multiple access interference), clock and data recovery, return-to-zero to nonreturn-to-zero conversion (for optical code-division multiple-access compatibility with digital logic), framing (for byte synchronization), and forward-error correction (FEC) using a (255, 239) Reed-Solomon decoder. The receiver more than doubles the number of supported users at a bit-error rate 10 10 . The receiver supports an information rate of 156.25 Mb/s. We performed the measurements at a bit rate of 167.4 Mb/s and a chip rate of 1.339 Gb/s (eight chips per bit) to account for FEC overhead. Index Terms-Clock and data recovery (CDR), forward-error correction (FEC), optical code-division multiple-access (OCDMA), optical fiber communications, optical receiver, Reed-Solomon (RS) codes.

This paper describes an integrated ISFETs instrumentation system in a 0.18 m 1-poly-6-metal CMOS process. The chip is able to compute the average of CMOS ISFETs' threshold voltages by using an averaging array employing global negative current feedback. In addition, neither reference voltage nor current is required to set up the sigma-delta modulator because the internal signal is converted and processed in the frequency domain. The chip operates at 3.3 V for the analog blocks and the digital input/output blocks, and at 1.8 V for the core digital logic. It achieves 8 bits accuracy under 80 W static power consumption. The die area is 2.6 mm 2 .

We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image.

A new pixel Front-End Integrated Circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

An important part of the undergraduate curriculum for both electrical engineering and computer science students is coverage of digital logic design. Typically, this is accomplished by both a lecture and lab course. The purpose of the lab course is to have the students develop practical design skills. Traditional digital logic design courses focus on logic gates. However, most contemporary practical

We present a new, analytical model for the SGFET that is suitable for hand calculations and time-efficient circuit simulations. Our model expresses the pull-in, pull-out voltages and the stable travel range in terms of the structural parameters and the moving gate position as a function of the gate voltage. Starting from our model, we discuss the influence of the structural parameters on the transistor characteristics and the potential of the SGFET for logic circuits. We also introduce the SGFET SRAM cell to demonstrate the use of our model and to illustrate the interest of the SGFET for ultra-low power applications. SGFET logic gates exhibit a significantly reduced off-state power dissipation and improved functionality as compared to CMOS gates.

Digital electronics is a fundamental course in electrical engineering and many information technology programs, as well as most other science programs. In this paper, we present web-based system aimed at teaching logic design concepts and practices for computer science and engineering students implemented using LabVIEW. Experiments, which include digital logic gates, combinational logic circuits, seven segment display, sequential logic and counters are easily constructed and performed, both in traditional and online setups. This course is as an example of how to integrate a combination of theory and lab experiments simultaneously in a blended learning environment, where lectures can present the material for students to access, and at the same time perform the experiments online into the curriculum.

ABSTRACT: This paper considers the design of a keyless digital security system using a hardware programming tool. The system uses a 4 x 4 keypad that allows users to enter four keystrokes as security password. These keystrokes are converted to BCD codes by the keypad encoder. The designed system comprises of two basic components fused together as a block (the Memory logic and the Security logic). The memory logic is the storage medium for the 4-keystrokes while the security logic compares entry keystrokes to keystrokes that are stored in the memory logic.

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.

This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-V t voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes.

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small-or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories. First, students have some difficulties in understanding the link between discrete and programmable design techniques. Second, using only a single PLD, students are not automatically forced to learn modular design skills, which is one of the required learning outcomes in electrical engineering (EE) curricula. To overcome these problems, an innovative laboratory is proposed in this paper. Each training board contains four complex PLDs (CPLDs) and peripherals. In the initial sessions, students implement designs in which CPLDs are programmed as standard SSI/MSI chips and interconnected to construct the target circuit. Then, an active learning technique is used: Students form groups of any size and can set themselves more complex problems and choose their design approach. The proposed laboratory was set up at the Technical University of Lodz, Lodz, Poland, and the first classes were given in the 2008-2009 academic year. The instructors' insights and design reports and feedback from students were gathered and analyzed. The results showed the effectiveness of the novel approach. Students were deeply involved in solving self-imposed problems. They learned "engineering imagination," modular design, and teamwork skills. Some groups went far beyond the requirements set by the instructor. However, an additional conclusion is that the "standard" approach should not be completely eliminated.