Designing a Testable System on a Chip

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design-for-testability methodologies are usually required for testing different cores. Another issue is test integration. The purpose of this paper is to present a hierarchical test scheme for SOC with heterogeneous core test and test access methods. A hierarchical test manager (HTM) is proposed to generate the control signals for these cores, taking into account the IEEE P1500 Standard proposal. A standard memory BIST interface is also presented, linking the HTM and the memory BIST circuit. It can control the BIST circuit with the serial or parallel test access mechanism. The hierarchical test control scheme has low area and pin overhead, and high flexibility. An industrial case using this scheme has been designed, showing an area overhead of only about 0.63%.

IEEE Transactions on Computers, 2002

AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

—This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of chips with the help of an additional built-in hardware structure inside the circuit. Test-per-scan Logic BIST structure includes Test pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role of test pattern generator in Logic BIST since it is more efficient than binary counters. MISR is commonly used as an output response analyzer which acts as an alternative to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to every structural element in BIST to improve the fault coverage of IC testing. The proposed structural architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 48) pro-grammable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan 6 for implementing them on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete form were implemented for PRPG and MISR design. All the designs were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

Computer Aided Design, 2000. …, 2000

Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. Being able to rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective, the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them.

2003

In the last few years, an increasing use of Programmable Logic Devices (PLDs) in the development of new embedded and systems-on-a-chip (SoC) solutions created the need of new test procedures for this kind of components. Several approaches, depending on the type of PLDs used, were proposed in the literature, addressing the test of the configurable logic array, the interconnection arrays

IEEE Micro, 2002

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes, 2009

The claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self-Test mechanism (BIST) a promising feature to be integrated in current IC flows. There are a lot of types of BIST: Memories BIST, Logical BIST (LBIST) and also some mechanisms used to test analog parts of circuit. Traditional LBIST uses on-chip hardware to generate all test patterns with a pseudo-randompattern-generator (PRPG) and analyze the output signature generated by a multiple-input-signature-register (MISR). This approach requires the insertion of extra test-points or storing information outside chip to enable achieving a test coverage >98%. Also generating all test stimuli implies in a sacrifice of test application time, which can be acceptable for some small systems to perform self-test during boot up but could become a negative aspect when testing System-on-chip (SOC) ICs. The current IC development flow insert scan chains and generates automatically scan tests patterns to achieve high fault coverage for manufacturing test. Scan data compression techniques have proven to be very useful for reducing test cost while reducing test data volume and test application time. This work proposes the reuse of compressed scan test patterns used during manufacturing test to implement a LBIST with the goal of testing the circuit when it is already in field. The proposed LBIST mechanism aims to uncover defects that could occur due to the wear out of the circuit. A scan test pattern based LBIST architecture and a semi-automatic development flow are proposed and validated in a real word SoC testcase.

Defect and Fault …, 2006

This paper describes a methodology of creating a built-in test system of a system on chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps ...

IEEE Transactions on Industrial Electronics, 2000