Academia.eduAcademia.edu

Figure 2 – uploaded by bob jenkins

See full PDFdownloadDownload figure
ing the pixel clock, another for supplying a memory clock for DRAM/SAM transfers, and a third for the sub-system board clock. Figure 2 shows a detailed block diagram of the logic/analog section of the chip. Figure 3 is a photo- graph of the chip, showing the DRAM, SAM, PLL, DAC and logic sections. 3. Test Methodology

Figure 2 ing the pixel clock, another for supplying a memory clock for DRAM/SAM transfers, and a third for the sub-system board clock. Figure 2 shows a detailed block diagram of the logic/analog section of the chip. Figure 3 is a photo- graph of the chip, showing the DRAM, SAM, PLL, DAC and logic sections. 3. Test Methodology

Related Figures (2)

design (LSSD) [8]. In this methodology, each storage ele- ment, such as an edge-triggered D flip-flop, incorporates a pair of level-sensitive d-latches connected to two non- overlapping clocks. These latches are connected in series throughout the design to form the scan chain. This dual- clock scheme eliminates concems about timing within the scan chain, and makes clock-gating logic testable. IBM ASIC methodology provides an option for designing cir- cuits with these conventional LSSD latches controlled by two non-overlapping clocks generated from a shared clock splitter. This clock splitter cell accepts an edge-triggered system clock, two level sensitive test clocks and a test-
design (LSSD) [8]. In this methodology, each storage ele- ment, such as an edge-triggered D flip-flop, incorporates a pair of level-sensitive d-latches connected to two non- overlapping clocks. These latches are connected in series throughout the design to form the scan chain. This dual- clock scheme eliminates concems about timing within the scan chain, and makes clock-gating logic testable. IBM ASIC methodology provides an option for designing cir- cuits with these conventional LSSD latches controlled by two non-overlapping clocks generated from a shared clock splitter. This clock splitter cell accepts an edge-triggered system clock, two level sensitive test clocks and a test-
testers with large amounts of memory to map the faults in a memory array and optimally choose the most efficient
testers with large amounts of memory to map the faults in a memory array and optimally choose the most efficient
Related topics:
VLSI testBuilt in self testDigital LogicSystem on a ChipDigital to Analog ConverterApplication Specific Integrated Circuit (ASIC)
580 California St., Suite 400
San Francisco, CA, 94104
© 2025 Academia. All rights reserved