Digital Logic

It is believed that the concept of integrated optical interconnect is a potential technological solution to alleviate some of the ever more pressing issues involved in exchanging data between cores in SoC architectures (inter-line crosstalk, latency, global throughput, connectivity and power consumption). This abstract summarises work carried out in the framework of the EU-funded PICMOS project on the quantitative comparison of optical interconnect to electrical interconnect in the context of on-chip data communication.

This study examines the validity of the Force Concept Inventory (FCI) in Ugandan secondary schools using Item Response Curves (IRCs) and provides a comparative evaluation of its effectiveness across different educational contexts. The survey focused on Senior Four students preparing for the Uganda Certificate of Education (UCE) examinations, with a representative sample of 941 students (aged 15-17) selected through a multi-stage sampling technique. The initial analysis employed Classical Test Theory (CTT) metrics before the detailed analysis of IRCs for the FCI items. The CTT evaluates item-level and whole test statistics like item difficulty level, discrimination index, and reliability. The CTT indices revealed that the FCI was highly challenging, with an average score of 5.76 out of 30 and a low-reliability coefficient (α = 0.15). Additionally, 73.3% of the items showed poor discrimination, and some distractors were ineffective. The detailed analysis of IRCs showed that several FCI items are inefficient in the context of the Ugandan education system. The IRCs also demonstrated a widespread choice of distractors for many items, with overall scores falling below the threshold indicative of a generally agreed-upon understanding of Newtonian physics. Comparative analysis from other global contexts studies suggests that language barriers, curriculum differences, and instructional methods influence student performance. These findings underscore the necessity of adapting the FCI tool to better fit local educational contexts and implementing additional instructional strategies to enhance conceptual understanding. A more culturally and contextually adapted diagnostic tool may improve physics education and better assess students' conceptual comprehension of force and motion within the region.

The Electrical Engineering microprocessor design course, like most design curriculum, allows students to develop practical engineering skills. At the University of Tulsa, we have augmented this to simulate a custom design house 1 . The students build 11 computer projects during the fall semester of the senior year. The projects begin with basic input / output, and then proceed through timers, serial communication to a PC, seven-segment displays, keyboards, liquid crystal displays, and analog conversion. These are performance-based projects. The mission is discussed in a lecture. The functional criteria are specified. Then it is up to the student to determine and purchase the hardware required. After that, the hardware must be integrated with the software. Each student must construct his own prototype on his schedule. The professor and assistants are available on a preset schedule to provide aid and to check the performance.

In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connectionbased packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the blocks activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.

Neurons carry out the many operations that extract meaningful information from sensory receptor arrays at the organism's periphery and translate these into action, imagery and memory. Within today's dominant computational paradigm, these operations, involving synapses, membrane ionic channels and changes in membrane potential, are thought of as steps in an algorithm or as computations. The role of neurons in these computations has evolved conceptually from that of a simple integrator of synaptic inputs until a threshold is reached and an output pulse is initiated, to a much more sophisticated processor with mixed analog-digital logic and highly adaptive synaptic elements.

Without loss of generality, level-sensitive latches are assumed to be active high and flip-flops are assumed to be negative edge-triggered. Under these assumptions, the active interval of a clock phase occurs when the phase IS high, and its latching edge is the falling transition 'A controlling value on a gate input is one which always determines the output value of the logic gate, regardless of its other inputs. A logic-one is the controlling value for ANDNAND gates, and a logic-zero is the controlling value for ORNOR gates. The XOR gate has no controlling value.

This paper outlines the implementation of a distributed billiard ball simulation in C++ using the MPI message passing interface. The implementation is heavily modelled after the discussions and algorithms found in [Lubachevsky 1991] and [MacKenzie and Tropper 1996]. [Lubachevsky 1991] outlines an efficient but non-distributed simple rigid disc simulator that assumes no friction, spin, et cetera, while [MacKenzie and Tropper 1996] discusses a distributed version using shared-memory. The implementation presented in this paper is slightly more complex in that it is distributed with no shared memory.

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 millions pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. Intensive calibration, tuning, timing optimization and monitoring resulted in the successful five years operation with good detector performance. The record breaking instantaneous luminosities of 7.7 • 10 33 cm -2 s -1 recently surpassed at the LHC generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors as an increase in the silicon leakage current and the change of the voltage required to fully deplete the sensor. The fourth pixel layer at the radius of 3.3 cm will be added during the long shutdown 2013-2014 together with the replacement of pixel services. Letter of Intent was submitted for the completely new Pixel Detector after 2023, capable to take data with extremely high leveled luminosities of 5 • 10 34 cm -2 s -1 at High Luminosity LHC.

• The integration of the hot-plug features inside EPICS has done successfully. • The solution allows the user to configure an entire system using the EPICS DB and st.cmd files. • This architecture supports system running with several boards at the same time. • The number of boards does not affect the stability of the system. • The GUI is automatically updated when a board is physically changed.

In this paper we show that the Walsh spectrum of Boolean functions can be analyzed by looking at algebraic properties of a class of Cayley graphs associated with Boolean functions. We use this idea to investigate the Walsh spectrum of certain special functions.

We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a transimpedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10 -9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.

Absrracr-This paper extends the polynominal time algorithm obtained in [7] to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. The extension of this paper allows one to find, in polynominal time, a minimal cardinality path set that both long and short covers these leads or gate inputs.

Iran Telecommunication Research Center, Tehran, Iran Islamic Azad University, Science and Research Branch, Tehran, Iran Summary A theoretical study of triple barrier resonant tunneling diode with multilayer GaAs/AlxGa1-xAs heterostructure is presented based on an exact ...

A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video Digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application Specific Integrated Circuit (ASIC) techniques are employed, using multiple DRAM macros with Built-in Self Test (BIST), full Level-Sensitive Scan Design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.

Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.

ABSTRACT The engineering profession in Australia has taken a leading role in promoting generic capabilities of engineering graduates (1). Since that time, Australia's three peak employer organisations have urged all education systems to enhance these skills through their programs (2, 3). Past efforts to promote generic skills (4) have foundered partly because no viable mechanism was established to link the development of these capabilities to the content and processes of teaching within disciplines. In this paper, we describe an approach to promoting problem solving in two topics in the first year of an engineering course. We describe the use of an assessment tool and some support materials for students and a process that used self-assessment followed by lecturer validation to grade student achievement in problem solving. We present the results of analyses of data gathered using the assessment tool. Engineering students at Flinders University undertake two topics in their first year, Circuits and Devices 1 and Digital Logic Design (one quarter of their studies), that start their technical education in electrical and electronic circuit theory. These topics provide both theoretical and practical skills in the analysis, use and design of electrical circuits, both analogue and digital, based on the operation and properties of their constituent devices. In addition to these technical topics, students also undertake Team Project and Communication Skills, a topic whose aim is to develop a range of transferable skills including engineering project planning and design, oral and written communication skills, and group-work skills. One of the many difficulties associated with teaching first year engineering students is an apparent lack of problem solving ability when dealing with challenging technical questions. They do not seem able to extend the knowledge learnt in their course to new problems. Many engineering educators have sought to develop generic capabilities in their students. Recent examples include Patrick and Crebert (5) and Johnston and McGregor (6). In this study, we used a problem solving skills assessment tool that had been developed and trialled in an earlier study (7). We provided students with a range of support materials1 designed to explain what generic capabilities were and why they were valued by industry. The materials also included an explanation of the model of problem solving that we implemented in this study. Importantly, we required students to assess their own problem solving performance using the assessment tool before submitting their assignments. Their assignments were marked as they had been in previous years, and in addition, their lecturer assessed explicitly students' problem solving performance using the assessment tool.

This book presents a new technology for programming FPGAs. The psC language and the Novakod Studio IDE make FPGA programming accessible to C++ developers. All you need is a little C++, and you will easily learn psC to program FPGAs. The psC compiler generates high quality VHDL code that can be inserted in any Vivado or Quartus project. In addition, the CYCLE-ACCURATE HIGH-LEVEL SIMULATOR gives you WYSIWYG (What You Simulate Is What You Get) on the real FPGA. A paperback edition is available on Amazon.

− − − −Application-specific or embedded systems with less than 16 processing cores are too small to use some kind of network on chip (NoC) for interconnection. On the other hand, a crossbar and related circuitry (arbiters, memory elements) are too expensive in terms of chip area. As only few pair-wise and collective communication patterns are mostly used in specific applications, we explore an interconnection network that can support only selected communication patterns and no others. The main contribution of the paper is designing of such networks without routers or arbiters, in a form of programmable combinational logic, with limited crossbar functionality. The interconnection network can be implemented by multiplexers or block RAMs on the FPGA chip at a very low cost. A functional decomposition of the related multiple-output Boolean function into a cascade of block RAM devices is aided by multi-terminal binary decision diagrams and is illustrated on examples.

Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper we study the routing constraints of Virtex devices and we propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of our proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements. Due to this, the design criterion that guides our architecture selections was the minimal Energy×Delay Product (EDP). The methodology is fully-supported by three new software tools, which belong to MEANDER Design Framework. Using a typical set of MCNC benchmarks, extensive comparison study in terms of several critical parameters proves the effectiveness of the derived interconnection network. More specifically, we achieve average Energy×Delay Product reduction by 63%, performance increase by 26%, reduction in leakage power by 21%, reduction in total energy consumption by 11%, at the expense of increase of channel width by 20%.

In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGAbased reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed.

Gottfried Leibniz embarked on a research program to prove all the Aristotelic categorical syllogisms by diagrammatic and algebraic methods. He succeeded in proving them by means of Euler diagrams, but didn't produce a manuscript with their algebraic proofs. We demonstrate how key excerpts scattered across various Leibniz's drafts on logic contained sufficient ingredients to prove them by an algebraic method --which we call the Leibniz-Cayley (LC) system-- without having to make use of the more expressive and complex machinery of first-order quantificational logic. In addition, we prove the classic categorical syllogisms again by a relational method --which we call the McColl-Ladd (ML) system-- employing categorical relations studied by Hugh McColl and Christine Ladd. Finally, we show the connection of ML and LC with Boolean algebra, proving that ML is a consequence of LC, and that LC is a consequence of the Boolean lattice axioms, thus establishing Leibniz's historical priority over George Boole in characterizing and applying (a sufficient fragment of) Boolean algebra to effectively tackle categorical syllogistic.

This paper describes a simulation to predict the susceptibility of an advanced avionics control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor, and it incorporates fault-tolerant techniques. The system being tested and the method of performing the transient-injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection. Logic errors Electrical transient Analog-digital simulation

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (Td-100 ps) GaAs digitaf IC'Swith up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evahrate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs K's should be about six times faster than Si IC'S. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLS1compatible in power and density. The experimental performance results are compared for the Ieadhg GSASlogic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as Td = 110 ps).

In this research Genetic Programming is applied to the synthesis of arbitrary logic expressions. As a new method of logic synthesis, this technique is uniquely advantageous in its flexibility for both problem applicability and optimization criterion. A number of experiments were conducted exploring this method with different types of logic gates and population sizes While complete function coverage is not guaranteed, the best experimental test results over eight randomly designed functions, of four to seven input variables, have produced logic equations with a 98.4% function coverage. In addition, the relation between the training set she for the Genetic Program and function coverage was also empirically explored. These experiments showed that only small training sets were necessary for function recognition.

The impact of the global economy has brought about significant changes in the traditional approaches adopted by manufacturing companies. In response to these changes, manufacturing entities have recognized the importance of key characteristics such as real-time adaptability to changes, prompt and high-quality responses to customer demands, and the enhancement of production processes through both hardware equipment and software modules. The evolution toward next-generation manufacturing systems has made the material handling system a pivotal component in modern manufacturing processes. Given the current landscape of the manufacturing industry, characterized by a wide array of products and the need for swift response times, there is a heightened demand for intelligent material handling systems. Meeting these demands necessitates the implementation of custombuilt systems, each requiring uniquely developed control software that addresses aspects such as flow control, product routings, and the layout and distribution of products. This paper aims to contribute to this evolving landscape by proposing the design and development of a "smart materials handling system." The system encompasses conveyors, robots, and sensors. Specifically, the conveyors are engineered to facilitate effortless and secure loading and unloading processes, facilitated by a robotic arm. To elevate the intelligence of the system, sensors are integrated to enable the identification and distribution of objects effectively.

CC-TEGAS3 is a time domain digital logic simulation and test generation system. Presently there are six primary modes of simulation with other modes in development. Modes one through three are for true value simulation only and are used for logic verification and design verification. Modes four through six correspond to modes one through three, respectively, but are for fault simulation. These later modes allow a user to simulate faults at either the logic verification level, (using assignable nominal element propagation delays), or at the design verification level using as signable minimummaximum delay times. Mode six represents one of the most accurate fault simulators yet to be implemented. The description, analysis, design conslderations, implementation techniques, and data structures used in the fault simulation modes of the CC-TEGAS3 system are the subject of this paper.

Fractional-order capacitors and memcapacitors have become a major research area in recent decades. Analog applications of both circuit elements are getting more common. In literature, the conformal fractional derivative (CFD) is getting lots of interest due to its easiness to use and to comprehend. Some supercapacitors have already been modeled with the conformal fractional derivative. Two-capacitor problem is an important problem in physics. Recently, a two-capacitor problem with a CFD capacitor and a linear timeinvariant (LTI) capacitor has been examined. To the best of our knowledge, a circuit, which is made of a CFD capacitor and a memcapacitor, has not been analyzed in the literature yet. In this study, a two-capacitor problem, a circuit, which consists of a CFD capacitor and a memcapacitor, has been examined using simulations for the first time in literature. It is found that the circuit is in ever transient state.

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This paper presents a concurrent simulation methodology for digital logic experimentation, which supports a multiple experiment environment for creating and maintaining scenarios of independent experiments without being exhaustive. It eficiently compresses multiple experiments in a single simulation and requires no pre-analysis of the circuit. In addition, scenarios can be created which allow experiments to interact with each other and spawn offspring experiments should new behaviors arise. The user initializes the simulation with independent experiments and the interactions are dynamically created if necessary. B y utilizing the similarity among experiments, we gain eftciency in storage and CPU time without resorting to parallel hardware. Providing this capability in digital logic simulators, allows more test cases to be run in less time, provides the exact location and causes of every behavior and can be used to track the signature paths of test patterns for coverage analysis. We will describe the multiple experiment algorithms, discuss the function list that makes dynamic interactions possible and report on its effectiveness for attacking an exhaustive simulation problem such as Multiple Stuck-at Fault simulations for digital logic. New directions for this type of testing methodology and applicability to other model types for creating experiment scenarios will also be discussed based on our results.

The last decades are characterized by constantly increasing interest of practically all industrialized countries of the world to the cast discrete reinforced aluminum matrix composite alloys (AMC’s). However, growth of volumes of industrial use of AMC’s for the present isn't adequate to technical and operational opportunities of these new materials. Further development of application of competitive AMC’s today requires conducting large-scale systematic researches and pilot projects in the following groups of problematic questions: the initial charge materials; technological processes of production; technological aspects of complex processing, including recycling; fundamental and applied research and development. Using as matrix alloys for AMC’s of low-grade and sub-standard waste of aluminum alloys requires development of new highly effective methods of their refinement, providing almost total absence of gases and products of a salt component of flux. Analysis of modern scientif...

We report device results from a wide bandwidth InP mesa-DHBT technology. In an effort to improve the manufacturability of submicron devices, the self-aligned base emitter junction is formed using dielectric sidewall spacers and a refractory base metal stack. Device performance has been optimized for high-speed digital and mixed-signal circuit applications. An HBT with emitter junctions dimensions of 0.7 × 3.0

A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.

Meeting the timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, we present a novel technique to speed up gate-level timing simulation that is based on Structurally Synthesized Binary Decision Diagrams (SSBDD), which have already found application as an efficient mathematical model to represent digital circuits. The new approach uses path delays instead of gate delays for tree-like subcircuits (macros). Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit, but only for outputs of macros. The macros are represented by SSBDDs, which enable a fast computation of delays for macros. We show that the speed-up of timing simulation is directly proportional to the average size of macros in the circuit. The new approach to speed up the timing simulation is supported by encouraging experimental results.

As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPGAs CAD flow to mitigate leakage power dissipation through the use of multi-threshold CMOS technologies to pack and place logic blocks that exhibit similar idleness close to each other so they can be turned off during their idle time. The modifications are integrated into the VPR flow and tested on several FPGA benchmarks using a CMOS 0.13µm dual-V th technology, resulting in an average leakage power savings of at least 20%.

FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. It is designed in a 130 nm CMOS process and is based on an array of 80 by 336 pixels, each 50×250 μm 2 for an overall size of about 19×20 mm 2. Each pixel consists of analog and synthesized digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides a solution to record hits timewalk-free. A mixture of techniques is used for yield enhancement. The chip periphery contains a control block, a command decoder and global memory, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which allows data transmission up to 160 Mb/s for the IBL.

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm 2) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

We present new experimental Windows 95/98/NT software for investigation of graph properties of boolean (in particular, Reed-Muller) logic with an equal number n of inputs and outputs (called movement functions). Realized at the input of an n-bit register, such functions create autonomous Finite State Machines (FSMs). TRACE software system allows the user to visualize State Transition Graphs (STGs) of the autonomous FSMs. Other features of TRACE help explore graph properties of function families. These families are produced by a generic function, differing from it only in the order of components, one operation, or one literal (this literal is complemented or replaced by another literal). The autonomous FSMs are used to implement economically next-state logic of realtime control units such as CPU controllers. A case study using TRACE to build economical, highly testable reversible counters based on linear Reed-Muller polynomials is given.

The automotive industry is one of the important industries which affected by raw materials of parts/spare parts. This work is applied research on the automotive products, such as main parts, and spare parts. The automotive products meet lot of problems, which come from certain causes such as environmental conditions. This work faces these problems and solves it, by taking some actions. Selecting raw materials which represent main causes of the problems and treatment it. This work uses analytical tool (Root-Cause Effect) to find out the root causes. Also, this work used new trends to improve the performance of raw material which uses in manufacturing of products such chemical treatment.

The reliability of computer-based systems implementing safety functions is a critical issue for the modernization and construction of nuclear power plants, in particular because software can usually not be proven to be entirely free of defects. The differences in regulation and safety justification principles between different countries restrict efficient co-operation and hinder the emergence of widely accepted best practices. This paper gives an introduction to an EU FP7 project HARMONICS (Harmonised Assessment of Reliability of Modern Nuclear I&C Software, 2011-2014) which has an overall objective to ensure that the nuclear industry has well founded and up-to-date methods and data for assessing software of computer-based safety systems.

This paper describes an integrated ISFETs instrumentation system in a 0.18 m 1-poly-6-metal CMOS process. The chip is able to compute the average of CMOS ISFETs' threshold voltages by using an averaging array employing global negative current feedback. In addition, neither reference voltage nor current is required to set up the sigma-delta modulator because the internal signal is converted and processed in the frequency domain. The chip operates at 3.3 V for the analog blocks and the digital input/output blocks, and at 1.8 V for the core digital logic. It achieves 8 bits accuracy under 80 W static power consumption. The die area is 2.6 mm 2 .

Approximate computing is an efficient approach for error-tolerant applications because it can trade off accuracy for power. Addition is a key fundamental function for these applications. We proposed a low-power yet high speed accuracy-configurable adder that also maintains a small design area. The proposed adder is based on the conventional carry look-ahead adder, and its configurability of accuracy is realized by masking the carry propagation at runtime. Compared with the conventional carry look-ahead adder, with only 14.5% area overhead, the proposed 16-bit adder reduced power consumption by 42.7% and critical path delay by 56.9% most according to the accuracy configuration settings, respectively. Furthermore, compared with other previously studied adders, the experimental results demonstrate that the proposed adder achieved the original purpose of optimizing both power and speed simultaneously without reducing the accuracy. Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs.

In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given.

We propose the encoding of memristive quantum dynamics on a digital quantum computer. Using a set of auxiliary qubits, we simulate an effective non-Markovian environment inspired by a collisional model, reproducing memristive features between expectation values of different operators in a single qubit. We numerically test our proposal in an IBM quantum simulator with 32 qubits, obtaining the pinched hysteresis curve that is characteristic of a quantum memristor. Furthermore, we extend our method to the case of two coupled quantum memristors, opening the door to the study of neuromorphic quantum computing in the NISQ era.