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are different for combinational and sequential logic [3]. that must be considered for measuring dynamic SEUs in logic circuits, and its effects

Figure 5 are different for combinational and sequential logic [3]. that must be considered for measuring dynamic SEUs in logic circuits, and its effects

Related Figures (22)

Fig. 1. Typical shape of the SE charge collection current at a junction exponential, time-dependent current pulse as shown in Fig. 1.
Fig. 1. Typical shape of the SE charge collection current at a junction exponential, time-dependent current pulse as shown in Fig. 1.
Fig. 2. Typical shape of the SE current pulse for advanced technologies
Fig. 2. Typical shape of the SE current pulse for advanced technologies
Fig. 3. Inverter string showing an n-hit at node ‘x’ This thesis proposes on-chip built-in testing for SETs and involves the electrical injection of pulses. Pulses that are electrically injected can either be current pulses or
Fig. 3. Inverter string showing an n-hit at node ‘x’ This thesis proposes on-chip built-in testing for SETs and involves the electrical injection of pulses. Pulses that are electrically injected can either be current pulses or
Fig. 4. Voltage transients at hit node ‘x’ and one node after hit node ‘y’
Fig. 4. Voltage transients at hit node ‘x’ and one node after hit node ‘y’
Fig. 6. Primary SET pulse parameters pulse offset with respect to the clock edge, as shown in Fig 6. primary parameters that one should be concerned about here are the pulse width and
Fig. 6. Primary SET pulse parameters pulse offset with respect to the clock edge, as shown in Fig 6. primary parameters that one should be concerned about here are the pulse width and
Fig. 7. Technique to create pulses of multiple widths based on delay set by the delay chain squal in duration to the delay in the path since the output of the X-OR remains at logic chain creates a voltage pulse at the output of the X-OR gate. The pulse width is almost
Fig. 7. Technique to create pulses of multiple widths based on delay set by the delay chain squal in duration to the delay in the path since the output of the X-OR remains at logic chain creates a voltage pulse at the output of the X-OR gate. The pulse width is almost
appropriate delay for the latch. Since the latch consists of two cross-connected NAND
appropriate delay for the latch. Since the latch consists of two cross-connected NAND
Fig. 9. Circuit to generate SETs of varying arrival times and pulse widths Single-event Transient Pulse-G enerate Circuit
Fig. 9. Circuit to generate SETs of varying arrival times and pulse widths Single-event Transient Pulse-G enerate Circuit
Implementation in a Self-Test Mechanism Fig. 10. A Linear Feedback Shift Register (LFSR) Single-event strikes that occur in space are absolutely unpredictable and occur at
Implementation in a Self-Test Mechanism Fig. 10. A Linear Feedback Shift Register (LFSR) Single-event strikes that occur in space are absolutely unpredictable and occur at
Fig. 13. Pulse width as a function of the current-starved inverter s control voltage voltage, the width and arrival of the pulse w.r.t the clock were changed.
Fig. 13. Pulse width as a function of the current-starved inverter s control voltage voltage, the width and arrival of the pulse w.r.t the clock were changed.
Fig. 14. Pulse-Generate circuit with a series of 4 current-starved inverter chain as delay elements layout shows the location of the Pulse-G enerate circuit in the fabricated IC.
Fig. 14. Pulse-Generate circuit with a series of 4 current-starved inverter chain as delay elements layout shows the location of the Pulse-G enerate circuit in the fabricated IC.
Fig. 15. Layout of fabricated IC; red oval indicates location of Pulse-Generate circuit can be killed by the output pad capacitance if it had to be measured on an oscilloscope,
Fig. 15. Layout of fabricated IC; red oval indicates location of Pulse-Generate circuit can be killed by the output pad capacitance if it had to be measured on an oscilloscope,
Fig. 16. Measurements taken on-chip with Pulse-Capture circuit gates, those less than about two to three times the propagation delay of a single stage
Fig. 16. Measurements taken on-chip with Pulse-Capture circuit gates, those less than about two to three times the propagation delay of a single stage
carried out for SE strikes on every node in the 1-bit adder for the 8 different input
carried out for SE strikes on every node in the 1-bit adder for the 8 different input
A similar but in-depth and exhaustive anaylsis was performed on the 4-bit
A similar but in-depth and exhaustive anaylsis was performed on the 4-bit
that the above described processes to identify insertion nodes has to be done cannot be broken down into simpler blocks that are repeated several times, requiring event strikes (both n-hits and p-hits) were simulated on every node of the circuit, for all
that the above described processes to identify insertion nodes has to be done cannot be broken down into simpler blocks that are repeated several times, requiring event strikes (both n-hits and p-hits) were simulated on every node of the circuit, for all
where it can be stored and could propagate to the rest of the circuit.
where it can be stored and could propagate to the rest of the circuit.
Related topics:
Biomedical EngineeringDigital CircuitsBuilt in self testDigital LogicRANDOM NUMBER GENERATOR
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