Real Time Operating Systems

Tests for avionics embedded systems are implemented using proprietary test languages. No standard has emerged and the set of existing test languages is heterogeneous. This is challenging for test solution providers, who have to accommodate the different habits of their clients. In addition, test exchange between aircraft manufacturers and equipment/system providers is hindered. To address these problems, we propose a model-driven approach for test implementation: test models are developed/maintained, with model-tocode transformations towards target executable test languages. This paper presents the test meta-model underlying the approach. It integrates the domain-specific concepts identified from an analysis of a sample of proprietary test languages. The test meta-model is the basis for building test model editors and templatebased automatic code generators, as illustrated by a demonstrator we developed.

The paper discusses the literature survey of RTOS (Real Time Operating Systems) and its contributions to the embedded world. RTOS is defined as a system in which the correctness of the system does not depend only on the logical results of computation but also on the time at which the results are produced. It has to perform critical tasks on priority basis keeping the context switching time minimum. It is often associated with few misconceptions & we have tried to throw some light on it. Since last 20 years, RTOS is undergoing continuous evolution and has resulted into development of many commercial RTOS products. We have selected few commercial RTOS of different categories of real-time applications and have discussed its real-time features. A comparison of the commercial RTOSs' is presented. We conclude by discussing the results of the survey and comparing the RTOS based on performance parameters.

In this paper novel technique for CPU scheduling in real time operating systems by using genetic algorithm (GA) is proposed. Proposed adaptive algorithm is a combination of existing dynamic priority driven algorithm i.e. Earliest Deadline First (EDF) and new genetic algorithm (GA) based scheduling algorithm. First we have developed GA based scheduling algorithm and tested it during both under loaded and overloaded condition. Initially, in underloaded condition EDF is used for scheduling and in overloaded condition system will change to a GA based scheduling algorithm .Thus our Adaptive algorithm uses the strong features of both algorithms and overcome their drawbacks. We have simulated, proposed adaptive algorithm along with both EDF and GA based algorithms for real time systems. %Success Rate and %Effective CPU Utilization are used as performance measuring criteria for all these 3 algorithms. The evaluation of results and comparison of our proposed adaptive CPU scheduling algorithm with EDF algorithm shows that the proposed adaptive algorithm is optimal and efficient during underloaded as well as overloaded situations compared to EDF.

The last decade a trend can be observed towards multi-processor Systems-on-Chip (MPSoC) platforms for satisfying the high computational requirements of modern multimedia applications. The research community has mainly focused on communication issues (e.g. bus vs. networks-on-chip). Real-time operating systems for MPSoCs however, have gotten very little attention. Existing techniques like rate-monotonic scheduling from the real-time community are rarely applicable, because contemporary high-performance media processors (like Cell, graphics processors) do not support preemption. Furthermore, rate-monotonic scheduling cannot deal with multiple (heterogeneous) processors, data dependencies, and dynamically varying execution times that characterize modern media applications. This paper proposes new techniques to manage the computational resources of MPSoCs at run-time. We compare a centralized resource manager (RM) to two versions (Credit based and Rate based) of a novel, more distributed RM. The distributed RMs are developed to cope with a larger number of processors as well as concurrently executing applications. Experiments show that our distributed resource managers are more scalable, deal better with application and user dynamics, and require less buffering, while effectively enforcing throughput constraints.

This paper describes a tool set for on-line and off-line runtime formal verification of system of systems (SoS) using rapid source-code instrumentation of complex C, C++, and Java applications. The tool set consists of two Eclipse plugins: an automatic source code instrumentation tool and an XML-to-JUnit log-file converter. The automatic instrumentation tool inserts code snippets in the source code of the system under test. During the SUT's execution the code snippets create a log stream (file or socket stream) in XML format. The XML-to-JUnit log-file converter transforms this stream into equivalent JUnit tests within the Eclipse environment. These test scenarios are then executed against statechart-assertion formal specifications, thereby performing runtime verification. The tool set enables runtime verification of formal specifications that contain real-time constraints and is capable of performing such verification for applications running on most popular real-time operating systems.

The complexity of middleware leads to complex Application Programming Interfaces (APIs) and semantics, supported by configurable components in the middleware. Those components are selected to provide the desired semantics. Yet, incorrect configuration can lead to faulty middleware executions, detected late in the development cycle. We use formals methods to tackle this problem. They allow us to find appropriate composition of middleware components and the use of their APIs, and to detect valid or faulty sequences. To provide reusable results, we modeled a canonical middleware architecture using Z. We propose a validation scenario to verify middleware's invariants. We define invariants to exhibit inconsistent usage of these APIs. The specification has been checked with the Z/EVES [13] theorem prover.

The Controller Area Network (CAN) has been adopted as the network communication technology of choice in many real-time application domains. Due to the ever increasing sophistication of contemporary embedded controllers, it becomes both possible and convenient to access this kind of network by means of a well-known and standard application programming interface instead of resorting to an ad hoc framework. This paper describes the addition of CAN support to the eCos embedded real-time operating system, from the device interface layer up to the extension of its network communication modules, based on Berkeley sockets.

In this paper is presented an automatic process of verification. We focus in the verification of scheduling analysis parameter. This proposal is part of process based on Model Driven Engineering to automate a Verification and Validation process of the software on board of satellites. This process is implemented in a software control unit of the energy particle detector which is payload of Solar Orbiter mission. From the design model is generated a scheduling analysis model and its verification model. The verification as defined as constraints in way of Finite Timed Automatas. When the system is deployed on target the verification evidence is extracted as instrumented points. The constraints are fed with the evidence, if any of the constraints is not satisfied for the on target evidence the scheduling analysis is not valid.

This formal research demonstration attempts to present an approach to develop and assess architecture and component-based systems based on specifying software architecture augmented by statecharts representing component behavioral specifications [1]. The approach is applied for the C2 style [2] and associated ADL and is supported within a quality-focussed environment, called Argus-I, which assists specification-based analysis and testing at both the component and architecture levels.

Commercial-Off-The-Shelf heterogeneous platforms provide immense computational power, but are difficult to program and to correctly use when real-time requirements come into play: A sound configuration of the operating system scheduler is needed, and a suitable mapping of tasks to computing units must be determined. Flawed designs may lead a suboptimal system configurations and thus to wasted resources, or even to deadline misses and failures. We propose YASMIN, a middleware to schedule end-user applications with real-time requirements in user space and on behalf of the operating system. YASMIN provides an easyto-use programming interface and portability. It treats heterogeneity on COTS heterogeneous embedded platforms as a first-class citizen: It supports multiple functionally equivalent task implementations with distinct extra-functional behaviour. This enables the system designer to quickly explore different scheduling policies and task-to-core mappings, and thus, to improve overall system performance. In this paper, we present the design and implementation of YASMIN and provide an analysis of the scheduling overhead on an Odroid-XU4 platform. Last but not least, we demonstrate the merits of YASMIN on an industrial use-case involving a Search & Rescue drone.

The automotive industry makes increasing usage of Simulink-based software development. Typically, automotive Simulink designs are analyzed using non-formal test methods, which do not guarantee the absence of errors. In contrast, formal verification techniques aim at providing formal guarantees or counterexamples that the analyzed designs fulfill their requirements for all possible inputs and parameters. Therefore, the automotive safety standard ISO 26262 recommends the usage of formal methods in safety-critical software development. In this paper, we report on the application of formal verification to check discrete-time properties of a Simulink model for a park assistant R&D prototype feature using the commercial Simulink Design Verifier tool. During our evaluation, we experienced a gap between the offered functionalities and typical industrial needs, which hindered the successful application of this tool in the context of model-based development. We discuss these issues and propose solutions related to system development, requirements specification and verification tools, in order to prepare the ground for the effective integration of computer-assisted formal verification in automotive Simulink-based development.

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In diesem Positionspapier wird die Eignung der UML 2.0 zur Modellierung von Bordnetzarchitekturen in der Automobilindustrie untersucht. Diese Untersuchung wird durch eine Gegenüberstellung relevanter Charakteristika von Fahrzeug-IT und Business-IT motiviert. Ein potentielles Problem bei dem Einsatz der UML 2.0 wird bei einer Betrachtung der Architektur-und Komponentenentwicklung in der Fahrzeug-IT sichtbar. Hieraus wird als Handlungsbedarf die Überprüfung der Integrierbarkeit der UML 2.0 mit etablierten, domänen-spezifischen Modellierungsnotationen abgeleitet. 1 Einleitung In diesem Positionspapier wird die Eignung der UML 2.0 zur Erstellung von Architekturen im Automotive-Kontext untersucht. Hierzu wird zunächst ein schematischer Überblick über die Architektur-und Komponentenentwicklung für Fahrzeugbordnetze gegeben. Dann werden Charakteristika der beiden Bereiche Fahrzeug-IT und Business-IT der Automobilindustrie gegenübergestellt. Anschließend werden Eigenschaften der UML 2.0 aufgeführt, die für bzw. gegen ihren Einsatz in der Fahrzeug-IT sprechen. Nachfolgend wird der Aspekt der Integration von Architekturund Komponentenentwicklung in der Fahrzeug-IT betrachtet. Hierbei steht eine Integration von Architekturmodellen, die mit UML 2.0 erstellt werden, und von Komponentenmodellen, die mit etablierten, domänen-spezifischen Modellierungsnotationen wie MATLAB/Simulink oder ASCET erstellt werden, im Vordergrund. Als Fazit resultiert ein Handlungsbedarf: Die Integrierbarkeit von UML 2.0-Modellen und MATLAB/Simulink-bzw. ASCET-Modellen soll überprüft werden. 1 2 Architekturentwicklung für Fahrzeugbordnetze Die nachfolgende Abbildung zeigt schematisch einzelne Schritte bei der Entwicklung von Fahrzeugbordnetzen. Dabei werden lediglich die Architektur-Entwicklung und die Komponenten-Entwicklung relativ detailliert betrachtet. Abbildung 1: Architektur-Entwicklung und Komponenten-Entwicklung für Fahrzeugbordnetze Zum Verständnis der Abbildung 1 sollen folgende Begriffsklärungen dienen:-Funktionsnetz-Architektur: Diese stellt gesamthaft, aber implementierungsunabhängig, die Menge der zu realisierenden Funktionen eines Bordnetzes dar. Zusätzlich ist die Kommunikation zwischen den einzelnen Funktionen grob beschrieben.-SW-Architektur: Diese stellt gesamthaft die SW-Komponenten zur Realisierung der Bordnetzfunktionen sowie ihre wechselseitige Kommunikation dar.-HW-Architektur: Diese stellt die Menge der Steuergeräte (= ECUs), der Busverbindungen zwischen den Steuergeräten und der Gateways (zur Datenübertragung zwischen verschiedenen Bussen) dar.

Faced with the increasing complexity of Real-Time Embedded Systems, Model Driven Engineering offers the possibility of developping frameworks in which transformations are used to generate either executable code or formal models. However, these transformations themselves are generally not formalized. Correctness of transformations could therefore be called into question. This paper proposes a formalization of a transformation step, namely: the composition of formal fragments describing the behavior of a real-time system. These fragments are described using an extension of the classical Time Petri Nets, where the notion of roles was added to perform the composition of the fragments. This formalization increases confidence in transformations.

When applications adapt their behavior to the requirements of the environment, their resource usage can change dramatically. The resource usage implies the services that the applications require from the operating system. Thus, the operating system must either provide all services that are totally required over time or reconfigure itself. Reconfiguration of the operating system means to support on demand services or the possibility to degrade services. We present an approach where we extend our offline customizable operating system in order to be dynamically reconfigurable during run-time. Additionally, we describe the procedure how the operating system is aware of the current required services. We claim that the resource usage between the applications and the operating system is optimized. Thus, we derive a self-optimizing real-time operating system (SO-RTOS). This work concentrates on the integration of the configurator, which models the design space and controles the low-level reconfiguration, and the resource manager, which is responsible for the timeliness and optimality. An optimization case study realized on a prototype validates our approach.

The design of TTCN-3 focused on extensions to address testing needs of modern telecom and datacom technologies and widen the applicability to many kinds of tests including performance tests. One of the most important features of TTCN-3 is the platform independence which allows testers to concentrate on the test specification while the complexity of the underlying platform (i.e., operating system, hardware configuration, etc.) is left behind the scene. As far as the test distribution is concerned, TTCN-3 provides the necessary language elements for distributed tests. This is however supported in a transparent fashion so that the same test may run either locally or distributed. The distributed execution of a test enables the execution of test components belonging to one test configuration on different computers (the test nodes), sharing thus a bigger amount of computational resources. Test distribution is a research challenge when it comes to the problem of how to distribute the test components efficiently on the test nodes. Specifically for load testing-a particular kind of performance test-we investigate strategies to distribute tests on heterogeneous hardware in order to use the hardware resources of the test nodes efficiently.

The automotive industry makes increasing usage of Simulink-based software development. Typically, automotive Simulink designs are analyzed using non-formal test methods, which do not guarantee the absence of errors. In contrast, formal verification techniques aim at providing formal guarantees or counterexamples that the analyzed designs fulfill their requirements for all possible inputs and parameters. Therefore, the automotive safety standard ISO 26262 recommends the usage of formal methods in safety-critical software development. In this paper, we report on the application of formal verification to check discrete-time properties of a Simulink model for a park assistant R&D prototype feature using the commercial Simulink Design Verifier tool. During our evaluation, we experienced a gap between the offered functionalities and typical industrial needs, which hindered the successful application of this tool in the context of model-based development. We discuss these issues and propose solutions related to system development, requirements specification and verification tools, in order to prepare the ground for the effective integration of computer-assisted formal verification in automotive Simulink-based development.

The automotive industry makes increasing usage of Simulink-based software development. Typically, automotive Simulink designs are analyzed using non-formal test methods, which do not guarantee the absence of errors. In contrast, formal verification techniques aim at providing formal guarantees or counterexamples that the analyzed designs fulfill their requirements for all possible inputs and parameters. Therefore, the automotive safety standard ISO 26262 recommends the usage of formal methods in safety-critical software development. In this paper, we report on the application of formal verification to check discrete-time properties of a Simulink model for a park assistant R&D prototype feature using the commercial Simulink Design Verifier tool. During our evaluation, we experienced a gap between the offered functionalities and typical industrial needs, which hindered the successful application of this tool in the context of model-based development. We discuss these issues and propose solutions related to system development, requirements specification and verification tools, in order to prepare the ground for the effective integration of computer-assisted formal verification in automotive Simulink-based development.

In this paper we present STELAE, a model-driven test development environment for avionics embedded systems, implemented on top of a real integration test platform. It is the result of an R&D project between two research laboratories and a test solution provider, aiming to introduce model-driven engineering methodologies and technologies for the development of tests. Our work was motivated by the multiplicity of proprietary test languages in this industrial context, which no longer respond to the stakeholder needs. We present the early prototype functionalities (test model definition, automatic code generation and execution) on a case study inspired from real-life. Our feedback on the used technologies concludes this paper.

In the verification of multitask software in embedded systems, general purpose model checkers do not inherently consider characteristics of the real time operating system, such as priority-based scheduling, priority inversion, and protocols for protecting shared memory resources. Since explicit-state model checkers generally explore all possible execution paths and task interleaving, this could potentially lead to exploring execution paths that are redundant, unnecessarily increasing verification complexity and hampering tractability. Based on this premise, in this work we investigate how one can improve the performance of explicit-state model checkers, such as SPIN, for the verification of multitask applications that target OSEK compliant real time operating systems.

ion representing the SUT behavior, while the grey-box MBT describes the model with details of the design information. White-box testing is not usually considered MBT [29]. Also with the increasing demand in software products, customers expect more reliable, efficient and a quality software product that contains advanced features and functionality. The competition between many companies forces the manufacturer to deliver the product with certain

The growing dependence of our society on increasingly complex software systems, makes software testing ever more important and challenging. In many domains, such as healthcare and transportation, several independent systems, forming a heterogeneous and distributed system of systems, are involved in the provisioning of endto-end services to users. However, existing testing techniques, namely in the model-based testing field, provide little tool support for properly testing such systems. Hence, in this paper, we propose an approach and a toolset architecture for automating the testing of end-to-end services in distributed and heterogeneous systems. The tester interacts with a visual modeling frontend to describe key behavioral scenarios, invoke test generation and execution, and visualize test results and coverage information back in the model. The visual modeling notation is converted to a formal notation amenable for runtime interpretation in the backend. A distributed test monitoring and control infrastructure is responsible for interacting with the components of the system under test, as test driver, monitor and stub. At the core of the toolset, a test execution engine coordinates test execution and checks the conformance of the observed execution trace with the expectations derived from the visual model. A real world example from the Ambient Assisted Living domain is presented to illustrate the approach.

Auch wenn ihr durch die Prägung des Begriffs "Model-Driven Architecture" (MDA) durch die OMG zusätzliche Aufmerksamkeit zugekommen ist, hat die modellbasierte Entwicklung in vielen Bereichen von der Geschäftsprozessmodellierung bis hin zur Beschreibung von eingebetteten Steuerungssystemen Anwendung gefunden und geht dabei in den eingesetzten Techniken und Verfahren über die Trennung von plattformunabhängigen und plattformspezifischen Systembeschreibungen und den Übergang dazwischen hinaus. Zentrales Merkmal der modellbasierten Entwicklung ist dabei der Einsatz von Modellen, die sich an der Problem-anstatt der Lösungsdomäne orientieren. Dies bedingt einerseits die Bereitstellung anwendungsorientierter Modelle (z.B. Matlab/Simulink-artige für regelungstechnische Problemstellungen, Statechart-artige für reaktive Anteile) und ihrer zugehörigen konzeptuellen (z.B. Komponenten, Signal, Nachrichten, Zustände) und semantischen Aspekte (z.B. synchroner Datenfluss, ereignisgesteuerte Kommunikation). Andererseits bedeutet dies auch die Abstimmung auf die jeweilige Entwicklungsphase, mit Modellen von der Anwendungsanalyse (z.B. Beispielszenarien, Schnittstellenmodelle) bis hin zur Implementierung (z.B. Bus-oder Task-Schedules, Implementierungstypen). Für eine durchgängige modellbasierte Entwicklung ist daher im Allgemeinen die Verwendung eines Modell nicht ausreichend, sondern der Einsatz einer Reihe von abgestimmten Modellen für Sichten und Abstraktionen des zu entwickelnden Systems (z.B. funktionale Architektur, logische Architektur, technische Architektur, Hardware-Architektur) nötig. Durch den Einsatz problem-statt lösungszentrierter Modelle kann in jedem Entwicklungsabschnitt von unnötigen Festlegungen abstrahiert werden, während besonders wichtige und kritische Aspekte explizit und frühzeitig modelliert werden (z.B. Zeit, Prioritäten oder Kommunikationsaspekte). Die dadurch ermöglichte Anwendung analytischer und generativer Verfahren auf diesen Modellen ermöglicht die effiziente Entwicklung hochqualitativer Software. Modellbasierte Vorgehensweisen haben gerade in der Softwareentwicklung in den letzten Jahren deutlich an Bedeutung gewonnen. Gerade im Bereich eingebetteter Software (z.B. Automotive oder Avionic Software Engineering) erfährt der Einsatz von domänenspezifischen Modellierungswerkzeugen in der Softwarenetwicklung zunehmend an Verbreitung. Wesentlich dazu haben dabei die Weiterentwicklung von Sprachen für aufgabenspezifische Modelle (z.B. synchroner Datenfluss) und dazugehörige Werkzeugen für spezialisierte Bereiche (z.B. Regelungs-und Steuerungsalgorithmen, Anlagensteuerung) und die Verbesserung der Ent-wicklungswerkzeuge, vor allem hinsichtlich Implementierungsqualität, Bedienkomfort und Analysemächtigkeit beigetragen. Trotzdem sind im Kontext der modellbasierten Entwicklung noch viele, auch grundlegende Fragen offen, insbesondere im Zusammenhang mit der Durchgängigkeit. Die in diesen Tagungsband zusammengefassten Papiere stellen zum Teil gesicherte Ergebnisse, Work-In-Progress, industrielle Erfahrungen und innovative Ideen aus diesem Bereich zusammen und erreichen damit eine interessante Mischung theoretischer Grundlagen und praxisbezogener Anwendung. V Genau wie beim ersten, im Januar 2005 erfolgreich durchgeführten Workshop sind damit wesentliche Ziele dieses Workshops erreicht: -Austausch über Probleme und existierende Ansätze zwischen den unterschiedlichen Disziplinen (insbesondere Elektro-und Informationstechnik, Maschinenwesen/Mechatronik und Informatik) -Austausch über relevante Probleme in der Anwendung/Industrie und existierende Ansätze in der Forschung -Verbindung zu nationalen und internationalen Aktivitäten (z.B. Initiative des IEEE zum Thema Model-Based Systems Engineering, GI-AK Modellbasierte Entwicklung eingebetteter Systeme, GI-FG Echtzeitprogrammierung, MDA Initiative der OMG) Die Themengebiete, für die dieser Workshop gedacht ist und fachlich sehr gut abgedeckt sind, sich dieses Jahr (mit Ausnahmen) aber sehr stark auf den automotiven Bereich konzentrieren, fokussieren auf Teilaspekte modellbasierter Entwicklung eingebetteter Softwaresysteme. Darin enthalten sind unter anderem: -Domänenspezifische Ansätze zur Modellierung von Systemen (z.B. Avionik, Railway, Automotive, Produktions-und Automatisierungstechnik) -Durchgängigkeit und Integration von Modellen für eingebettete Systeme -Modellierung spezifischer Eigenschaften eingebetteter Systeme (z.B. Echtzeiteigenschaften, Robustheit/Zuverlässigkeit, Ressourcenmodellierung) -Konstruktiver Einsatz von Modellen (Generierung und Evolution) -Modellbasierte Validierung und Verifikation Das Organisationskomitee ist der Meinung, dass mit den Teilnehmern aus Industrie, Werkzeugherstellern und der Wissenschaft die bereits 2005 erfolgte Community-Bildung erfolgreich weitergeführt wurde, und damit demonstriert, dass eine solide Basis zur Weiterentwicklung des noch jungen Felds modellbasierter Entwicklung eingebetteter Systeme existiert. Die Durchführung eines erfolgreichen Workshops ist ohne vielfache Unterstützung nicht möglich. Wir danken daher den Mitarbeitern von Schloss Dagstuhl und natürlich unseren Sponsoren.

The design of TTCN-3 focused on extensions to address testing needs of modern telecom and datacom technologies and widen the applicability to many kinds of tests including performance tests. One of the most important features of TTCN-3 is the platform independence which allows testers to concentrate on the test specification while the complexity of the underlying platform (i.e., operating system, hardware configuration, etc.) is left behind the scene. As far as the test distribution is concerned, TTCN-3 provides the necessary language elements for distributed tests. This is however supported in a transparent fashion so that the same test may run either locally or distributed. The distributed execution of a test enables the execution of test components belonging to one test configuration on different computers (the test nodes), sharing thus a bigger amount of computational resources. Test distribution is a research challenge when it comes to the problem of how to distribute the test components efficiently on the test nodes. Specifically for load testing-a particular kind of performance test-we investigate strategies to distribute tests on heterogeneous hardware in order to use the hardware resources of the test nodes efficiently.

The design of control units of modern processors is quite complex due to many speed-up techniques like pipelining and out-oforder execution. The existing approaches to formal verification of processor designs are applicable to very high level descriptions that ignore timing details of control signals. In this paper, we propose an approach for verification of detailed design of processors. Our approach suggests the use of Esterel language which has rich constructs for succinct and modular description of control. The Esterel simulation tool Xes and verification tools Xeve and FcTools can be used effectively to catch minor bugs as well as subtle timing errors. As an illustration, we have developed an Esterel implementation of DLX pipeline control and verified certain crucial properties.

There have been several efforts on run-time mapping of applications on Multiprocessor-Systems-on-Chip (MP-SoCs). These traditional efforts perform either on-the-fly processing or use design-time analyzed results. However, on-the-fly processing often leads to low quality mappings, and design-time analysis becomes computationally costly for large-size problems and require huge storage for large number of applications. In this paper, we present a novel run-time mapping approach, where identification of an efficient mapping for a use-case is done by the online execution trace analysis of the active applications. The trace analysis facilitates for fast identification of the mapping while optimizing for the system resource usage and throughput of the active applications, leading to reduced energy consumption as well. By rapidly identifying the efficient mapping at run-time, the proposed approach overcomes the mappings' exploration time bottleneck for large-size problems and their storage overhead problem when compared to the traditional approaches. Our experiments show that on average the exploration time to identify the mapping is reduced 14× when compared to stateof-the-art approaches and storage overhead is reduced by 92%. Additionally, energy and resource savings are achieved along with identification of high quality mapping. Index Terms-Embedded Systems, Multiprocessor-Systems-on-Chip (MPSoCs), run-time mapping, design space exploration, throughput constraint I. INTRODUCTION A PPLICATION mapping on Multiprocessor-Systems-on-Chip (MPSoCs) has been identified as one of the most important problems in embedded systems design [1]-[3]. Under dynamic workloads, run-time mapping is required in order to optimize for performance and energy consumption towards fulfilling the end user demands. The run-time mapping can be accomplished either with or without previously analyzed results. For mapping without previously analyzed results, i.e.,

This paper describes a tool set for on-line and off-line runtime formal verification of system of systems (SoS) using rapid source-code instrumentation of complex C, C++, and Java applications. The tool set consists of two Eclipse plugins: an automatic source code instrumentation tool and an XML-to-JUnit log-file converter. The automatic instrumentation tool inserts code snippets in the source code of the system under test. During the SUT's execution the code snippets create a log stream (file or socket stream) in XML format. The XML-to-JUnit log-file converter transforms this stream into equivalent JUnit tests within the Eclipse environment. These test scenarios are then executed against statechart-assertion formal specifications, thereby performing runtime verification. The tool set enables runtime verification of formal specifications that contain real-time constraints and is capable of performing such verification for applications running on most popular real-time operating systems.

This paper compares several approaches for implementing multi-threaded servers in a distributed environment using the thread-encapsulation library of the ACE object-oriented toolkit. It designs, implements, measures and compares the performance of different single-threaded and multi-threaded server architectures taking into account various factors, such as execution overheads and consumption of shared system resources. It is shown that in certain system architectures, multi-threading can improve the overall performance of the system, by allowing for a more efficient use of the hardware resources.

In order to achieve the highest safety integrity levels, ISO26262 recommends the use of formal methods for various verification activities, throughout the lifecycle of safety-related embedded systems for road vehicles. Since formal methods are known to be difficult to use, one of the main challenges raised by these ISO26262 requirements is to find cost-effective approaches for being compliant with them. This paper proposes an approach for requirements formal verification where formal methods, languages, and tools are only minimally exposed to the user, and are integrated into one of the commonly used system modeling environments based on SysML. This approach does not require particular expertise in formal methods still allowing to apply them. Hence, personnel training costs and development costs should be kept limited. The proposed approach has been implemented as a plugin of the Topcased environment. Although it is limited to discrete system models, it has been successfully experimented on an industrial use case.

There have been several efforts on run-time mapping of applications on Multiprocessor-Systems-on-Chip (MP-SoCs). These traditional efforts perform either on-the-fly processing or use design-time analyzed results. However, on-the-fly processing often leads to low quality mappings, and design-time analysis becomes computationally costly for large-size problems and require huge storage for large number of applications. In this paper, we present a novel run-time mapping approach, where identification of an efficient mapping for a use-case is done by the online execution trace analysis of the active applications. The trace analysis facilitates for fast identification of the mapping while optimizing for the system resource usage and throughput of the active applications, leading to reduced energy consumption as well. By rapidly identifying the efficient mapping at run-time, the proposed approach overcomes the mappings' exploration time bottleneck for large-size problems and their storage overhead problem when compared to the traditional approaches. Our experiments show that on average the exploration time to identify the mapping is reduced 14× when compared to stateof-the-art approaches and storage overhead is reduced by 92%. Additionally, energy and resource savings are achieved along with identification of high quality mapping. Index Terms-Embedded Systems, Multiprocessor-Systems-on-Chip (MPSoCs), run-time mapping, design space exploration, throughput constraint I. INTRODUCTION A PPLICATION mapping on Multiprocessor-Systems-on-Chip (MPSoCs) has been identified as one of the most important problems in embedded systems design [1]-[3]. Under dynamic workloads, run-time mapping is required in order to optimize for performance and energy consumption towards fulfilling the end user demands. The run-time mapping can be accomplished either with or without previously analyzed results. For mapping without previously analyzed results, i.e.,

A key requirement for the development of safety-critical systems is the correctness of the tools used in their development process. Standards such as DO-178B mandate the qualification of tools used in the software engineering process of the systems to be certified at the highest levels of criticality. On the other hand, the increasing complexity of software requires the use of methodologies such as Model Based Development (MBD) that are highly tool intensive. MBD employs a suite of tools such as modeltranslators, code-generators, optimizers, simulators, etc., that can collectively be referred to as model-processors. A model-processor accepts a model in one language, and outputs a processed model in a possibly different language. Due to the increasing sophistication in modern modeling languages, model-processors are prone to implementation errors. Also, they are continuously evolving, resulting in differences in their behaviour across different releases. Our objective is to address t...

First-generation CORBA middleware was reasonably successful at meeting the demands of applications with besteffort quality of service (QoS) requirements. Supporting applications with more stringent QoS requirements poses new challenges for next-generation real-time CORBA middleware, however. This paper provides three contributions to the design and optimization of real-time CORBA middleware. First, we outline the challenges faced by real-time Object Request Broker (ORB) implementers, focusing on requirements for efficient, predictable, and scalable concurrency, demultiplexing, and protocol processing in CORBA's ORB Core and Object Adapter components. Second, we describe how TAO, our real-time CORBA implementation, addresses these challenges by applying key ORB optimization principle patterns, which are rules for avoiding common design and implementation problems that can degrade the efficiency, scalability, and predictability of complex systems. Third, we present the results of benchmarks that evaluate the impact of TAO's patterns and design strategies empirically. Our results indicate that it is possible to develop highly configurable, adaptable, and standard-compliant ORBs that can meet the QoS requirements of many real-time applications. A key contribution of our work is to demonstrate that the ability of CORBA ORBs to support real-time systems is largely an implementation detail. In particular, relatively few changes are required to the standard CORBA reference model and programming API to support real-time applications.

During the last two years, EDISOFT's RTEMS CENTRE team [1], jointly with the European Space Agency and with the support of the worldwide RTEMS community [2], have been developing an activity to facilitate the qualification of the real-time operating system RTEMS (Real-Time Operating System for Multiprocessor Systems). This paper intends to give a high level visibility of the progress and the results obtained in the RTEMS Improvement [3] activity. The primary objective [4] of the project is to improve the RTEMS product, its documentation and to facilitate the qualification of RTEMS for future space missions, taking into consideration the specific operational requirements. The sections below provide a brief overview of the RTEMS operating system and the activities performed in the RTEMS Improvement project, which includes the selection of API managers to be qualified, the tailoring process, the requirements analysis, the reverse engineering and design of the RTEMS, the quality ass...

The efforts spent on testing are enormous due to the continuing quest for better software quality, and the ever growing complexity of software systems. The situation is aggravated by the fact that the complexity of testing tends to grow faster than the complexity of the systems being tested, in the worst case even exponentially. Whereas development and construction methods for software allow the building of ever larger and more complex systems, there is a real danger that testing methods cannot keep pace with construction, hence these new systems cannot be sufficiently fast and thoroughly be tested. This may seriously hamper the development of future generations of software systems. One of the new technologies to meet the challenges imposed on software testing is model-based testing. Models can be utilized in many ways throughout the product life-cycle, including: improved quality of specifications, code generation, reliability analysis, and test generation. This paper will focus on...

We present a high-level method for rapidly and accurately estimating energy and performance overhead of Real-Time Operating Systems. Unlike most other approaches, which rely on Transaction-Level Modeling (TLM), we infer the information we need directly from executing the algorithmic specification, without needing to build any high-level architectural model. We distinguish two main components in our approach: first, an accurate one-time pre-characterization of the main RTOS functionalities in terms of energy and cycles; second, the development of an algorithm to rapidly predict the occurrences of such RTOS functionalities. Finally, we demonstrate the feasibility of our approach by comparing it against gate level for accuracy and against TLM for speed. We obtain a worst-case energy error of 12% against a mean speedup of 36X.

The Gamma Statechart Composition Framework is an integrated tool to support the design, verification and validation as well as code generation for component-based reactive systems. The behavior of each component is captured by a statechart, while assembling the system from components is driven by a domain-specific composition language. Gamma automatically synthesizes executable Java code extending the output of existing statechart-based code generators with composition related parts, and it supports formal verification by mapping composite statecharts to a back-end model checker. Execution traces obtained as witnesses during verification are back-annotated as test cases to replay an error trace or to validate external code generators. Tool demonstration video: https://youtu.be/ng7lKd1wlDo CCS CONCEPTS • Theory of computation → Verification by model checking; • Software and its engineering → System modeling languages; Formal software verification;

This paper proposes a Real-Time Operating System kernel for the 32-bit Leon3 processor. A system is said to be Real Time if it is required to complete its work and deliver its services on time. In a real-time system the correctness of its output, is an important factor, depends not only the logical computations carried out but also the time at which the results were delivered to the external interface. A Real time operating system (RTOS) is a class of operating system intended for real time applications. The requirements for developing an RTOS include RMS scheduling algorithm, file management scheme, interrupt handling, Timer etc. Most of these functions are in POSIX 1003.1b compliant. tsim simulator is used for compilation and debugging..

This paper proposes a Real-Time Operating System kernel for the 32-bit Leon3 processor. A system is said to be Real Time if it is required to complete its work and deliver its services on time. In a real-time system the correctness of its output, is an important factor, depends not only the logical computations carried out but also the time at which the results were delivered to the external interface. A Real time operating system (RTOS) is a class of operating system intended for real time applications. The requirements for developing an RTOS include RMS scheduling algorithm, file management scheme, interrupt handling, Timer etc. Most of these functions are in POSIX 1003.1b compliant. tsim simulator is used for compilation and debugging..

The aim of this article is to present a modeldriven approach proposed by the SPaCIFY project for spacecraft on-board software development. This approach is based on a formal globally asynchronous locally synchronous language called Synoptic, and on a set of transformations allowing code generation and model

The efforts spent on testing are enormous due to the continuing quest for better software quality, and the ever growing complexity of software systems. The situation is aggravated by the fact that the complexity of testing tends to grow faster than the complexity of the systems being tested, in the worst case even exponentially. Whereas development and construction methods for software allow the building of ever larger and more complex systems, there is a real danger that testing methods cannot keep pace with construction, hence these new systems cannot be sufficiently fast and thoroughly be tested. This may seriously hamper the development of future generations of software systems. One of the new technologies to meet the challenges imposed on software testing is model-based testing. Models can be utilized in many ways throughout the product life-cycle, including: improved quality of specifications, code generation, reliability analysis, and test generation. This paper will focus on...

Scheduling decision for real-time embedded software applications has a great impact on system performance and, therefore, is an important issue in RTOS design. Moreover, it is highly desirable to have the system designer able to evaluate and select the right scheduling policy at high abstraction levels, in order to allow faster exploration of the design space. In this paper, we address this problem by introducing an abstract RTOS model, as well as a new approach to refine an unscheduled high-level model to a high-level model with RTOS scheduling. This approach is based on SystemC language and enables the system designer to quickly evaluate different dynamic scheduling policies and make the optimal choice in early design stages. Furthermore, we present a case of study where our model is used to simulate and analyze a telecom system.

This paper presents a formal model-based methodology to support railway engineers in the design of safe electronic urban railway control systems. The purpose of our research is to overcome the deficiencies of existing traditional design methodologies, namely the incompleteness and the potential presence of contradictions in the system specification resulting from non-formal development techniques. We illustrate the application of the methodology via a case study of a tram-road level crossing protection system. It was chosen partly because it has a simple architecture and a small number of elements, thus it fits the scope limitations of this article. At the same time, it is suitable for presenting all essential features of our methodology. The proposed solution provides a specification/verification environment that facilitates the construction of correct, complete, consistent, and verifiable functional specifications during the development, while hiding all the formal method-related ...

As applications grow increasingly complex, so do the complexities of the microcontroller-based embedded devices such as cell phones, digital TVs, smart cars, washing machines and so on. Although these recent applications operate in hard constraint conditions, embedded systems are required to respond to external events in a shortest possible time. In this paper, we present a variety of scheduling algorithms for a single microcontroller-based embedded devises with static and dynamic priorities and show a study on different parameters, such as computing time, burst time, waiting times and average turnaround time for each algorithm. This study aims to select the appropriate operating system for the particular situation and also to conceive new solutions that can improve several features such as waiting times and average turnaround time.

With the proliferation of scheduling algorithms there i s a g r owing need to test these schedulers for their validity not just at design time but also as the system evolves. This implies that the schedulability analysis has to be r obust. In this study, we identify a few often posed questions that address the robustness of schedulability analyses. First these questions are d e alt in the context of uniprocessor systems and then we handle some of their extensions in a more general context of end-to-end systems. We show that these questions are closely related to a more general problem. We present a solution to this problem. An intuitive proof of correctness and optimality of the solution technique are presented.

Embedded systems are typically implemented as a set of communicating components some of which are implemented in hardware and some of which are implemented in software. Usually many software components share a processor. A real-time operating system (RTOS) is used to enable sharing and provide a communication mechanism between components. Commercial RTOSs are available for many popular micro-controllers. Using them provides significant reduction in design time and often leads to better structured and more maintainable systems. However, since they have to be quite general, they are not efficient enough for many applications, either in memory usage or in run times. Thus, it is often the case that RTOSs are hand coded by an expert for a particular application. This approach is obviously slow, expensive and error-prone.In this paper we propose an alternative where a RTOS is automatically generated based on a high-level description of the system. RTOSs created in our approach offer an ea...

ion representing the SUT behavior, while the grey-box MBT describes the model with details of the design information. White-box testing is not usually considered MBT [29]. Also with the increasing demand in software products, customers expect more reliable, efficient and a quality software product that contains advanced features and functionality. The competition between many companies forces the manufacturer to deliver the product with certain

Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogenous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized-our framework also includes energy reduction techniques utilizing dynamic power management. Experimental results on a realistic multi-mode multi-media terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.

International audience—The development of real-time embedded systems is quite complex because of the wide range of execution platforms and of the importance of non-functional requirements. Further-more, Model Driven Engineering is particularly suitable for han-dling the diversity of implementation targets. Therefore, several real-time embedded systems development suites leverage Model Driven Engineering by automatically generating platform-specific code from high-level design models. Such tools may also take non-functional requirements into account by integrating verification activities. These activities typically rely on the generation of formal models from the same high-level design descriptions used for code generation. However, few tool suites support both code and formal model generation. Furthermore, among these, most overlook real-time operating systems mechanisms. Therefore, both code and formal models generated by these tool suites may not behave as specified in the high-le...

As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning...