César Marcon

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Papers by César Marcon

Exploration and Analysis of Combinations of Hamming Codes in 32-bit Memories

arXiv (Cornell University), Jun 28, 2023

Reducing the threshold voltage of electronic devices increases their sensitivity to electromagnet... more Reducing the threshold voltage of electronic devices increases their sensitivity to electromagnetic radiation dramatically, increasing the probability of changing the memory cells' content. Designers mitigate failures using techniques such as Error Correction Codes (ECCs) to maintain information integrity. Although there are several studies of ECC usage in spatial application memories, there is still no consensus in choosing the type of ECC as well as its organization in memory. This work analyzes some configurations of the Hamming codes applied to 32-bit memories in order to use these memories in spatial applications. This work proposes the use of three types of Hamming codes: Ham(31,26), Ham(15,11), and Ham(7,4), as well as combinations of these codes. We employed 36 error patterns, ranging from one to four bitflips, to analyze these codes. The experimental results show that the Ham(31,26) configuration, containing five bits of redundancy, obtained the highest rate of simple error correction, almost 97%, with double, triple, and quadruple error correction rates being 78.7%, 63.4%, and 31.4%, respectively. While an ECC configuration encompassed four Ham(7.4), which uses twelve bits of redundancy, only fixes 87.5% of simple errors. Additionally, we performed a relative reliability analysis among the analyzed codes over 3500 days of operation.

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Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC

Symposium on Integrated Circuits and Systems Design, Aug 1, 2016

One of the major problems in Depth Modeling Mode 1 (DMM-1) hardware design is the large memory ar... more One of the major problems in Depth Modeling Mode 1 (DMM-1) hardware design is the large memory area required for storing all wedgelet patterns. This work presents four energy-aware light-weight coding techniques to reduce the memory usage and power dissipation. Experimental results show that the proposed techniques are capable of reaching a compression rate of 76.9%, representing a reduction of 140 Kbits. In the DMM-1 hardware design, this compression rate results in smaller memory, fewer memory accesses and, thus a power dissipation decrease, reaching 678 mW for ST 65nm standard cells technology.

Tile Adaptation for Workload Balancing of 3D-HEVC Encoder in Homogeneous Multicore Systems

IEEE Transactions on Circuits and Systems I-regular Papers, May 1, 2020

In wireless sensor networks (WSNs), the base station (BS) is a critical sensor node whose failure... more In wireless sensor networks (WSNs), the base station (BS) is a critical sensor node whose failure causes severe data losses. Deploying multiple fixed BSs improves the robustness, yet requires all BSs to be installed with large batteries and large energy-harvesting devices due to the high energy consumption of BSs. In this paper, we propose a scheme to coordinate the multiple deployed BSs such that the energy supplies required by individual BSs can be substantially reduced. In this scheme, only one BS is selected to be active at a time and the other BSs act as regular sensor nodes. We first present the basic architecture of our system, including how we keep the network running with only one active BS and how we manage the handover of the role of the active BS. Then, we propose an algorithm for adaptively selecting the active BS under the spatial and temporal variations of energy resources. This algorithm is simple to implement but is also asymptotically optimal under mild conditions. Finally, by running simulations and real experiments on an outdoor testbed, we verify that the proposed scheme is energy-efficient, has low communication overhead and reacts rapidly to network changes.

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Configurable Fast Block Partitioning for VVC Intra Coding Using Light Gradient Boosting Machine

IEEE Transactions on Circuits and Systems for Video Technology, Jun 1, 2022

Reflect3d: An Adaptive and Fault-Tolerant Routing Algorithm for Vertically-Partially-Connected 3D-NoC

The combined benefits of the Three-Dimensional (3D) and Network-on-Chip (NoC) schemes enable desi... more The combined benefits of the Three-Dimensional (3D) and Network-on-Chip (NoC) schemes enable designing a high-performance system in a limited chip area. The 3D-NoC major advantages are the average reductions of wire length and delay, resulting in lower power dissipation and higher performance. However, 3D-NoCs suffer from some reliability issues, such as the 3D-IC manufacturing variability. The low yield of vertical connection harms the design of 3D die stacks with many Through Silicon Via (TSV). Vertically-Partially-Connected NoCs have been gaining relevance to reduce the number of TSV links. This work introduces Reflect3d, an adaptive, scalable, and highly resilient routing algorithm targeting partially and vertically connected 3D-NoCs to route packets under such conditions. Reflect3d separates virtual channels in four reflected virtual networks to search for vertical connections dynamically and progressively, guaranteeing packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. The experimental results show that Reflect3d can ensure high performance in terms of latency, achieving more valid paths and better cost-effectiveness when compared to related work. Furthermore, the hardware synthesis performed using a commercial 28nm technology library shows few area and power overheads compared to other state-of-the-art routing algorithms.

3D-HEVC Background

Springer eBooks, Aug 21, 2019

This chapter provides background about Three-Dimensional High Efficiency Video Coding (3D-HEVC) d... more This chapter provides background about Three-Dimensional High Efficiency Video Coding (3D-HEVC) depth map encoding. Initially, the 3D-HEVC encoding structure is defined, relating its frame to a quadtree-like structure. The algorithms used in the intra-frame prediction of depth maps are described in detail, allowing a comparative understanding regarding the predictability of texture coding. Next, inter-frame and inter-view prediction algorithms are presented, followed by the description of standard tools used in the intra-frame, inter-frame, and inter-view predictions. This chapter finishes by describing the Common Test Conditions (CTC), which must be followed to generate results comparable to other related works.

An efficient, low-cost ECC approach for critical-application memories

Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to... more Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy is required for its implementation, becoming a problem if applied in application where resources are scarce. This article presents the implementation and evaluation of the Matrix Region Section Code (MRSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. The experimental results measuring error coverage composed by detection and correction analysis, area, power and delay overheads have shown that MRSC is an excellent option to counteract with MCUs.

Light Gradient Boosting Machine Configurable Fast Block Partitioning for Luminance

Springer eBooks, 2022

Heuristic-Based Fast Block Partitioning Scheme for Chrominance

Springer eBooks, 2022

Fast Partitioning Decision Scheme for Versatile Video Coding Intra-Frame Prediction

This paper presents a fast partitioning decision scheme for Versatile Video Coding (VVC) intra pr... more This paper presents a fast partitioning decision scheme for Versatile Video Coding (VVC) intra prediction. VVC adopts the tree coding block structure named Quadtree with nested Multi-Type (QTMT), which significantly improves the coding efficiency at the cost of a high computational effort, limiting its adoption for real applications. Thus, we developed a scheme that encompasses two strategies exploring the features of the current block and the encoding context through the selected intra prediction mode to skip unnecessary evaluations of binary and ternary partitions. Experimental results, obtained with VVC Test Model 5.0 and considering the Common Test Conditions (CTC) under All-Intra (AI) encoder configuration, demonstrated that the proposed scheme achieves 31.41% of coding time saving, on average, with negligible coding efficiency loss.

Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA

Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications

Newest technologies of integrated circuits manufacture allow billions of transistors arranged in ... more Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip, which requires a communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). As the technology scales down, the probability of Multiple Cell Upsets (MCUs) increases, being Error Correction Code (ECC) the most used technique to protect stored information against MCUs. NoC buffers are components that suffer from MCUs induced by diverse sources, such as radiation and electromagnetic interference. Thereby, applying ECCs in NoC buffers may come as a solution for reliability issues, although increasing the design cost and requiring a buffer with higher storage capacity. This paper proposes an optimized buffer using an Extended Hamming code to deal with MCUs and enhance the protected information storage, pursuing to reduce the area and power required for ECC implementation. We guide the optimized buffer evaluation by measuring the fault tolerance efficiency, buffer area, power overhead and performance of the proposed technique. All tests included the comparison with a non-optimal appliance of ECC in a NoC buffer. The results show the proposed technique reduces the area and power overhead in buffers with ECC and allows a considerable fault tolerance against MCUs with a small performance impact.

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DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard

Journal of Electronic Imaging, Nov 30, 2016

Abstract. Depth modeling mode 1 (DMM-1) processes its prediction unit (PU) without taking into ac... more Abstract. Depth modeling mode 1 (DMM-1) processes its prediction unit (PU) without taking into account its neighborhood. However, an extensive analysis of neighbor pattern selection showed that the processing PU could use the same pattern of its neighbors or an adaptation of these patterns. Therefore, this work proposes the DMM-1 fast pattern selector (DFPS) algorithm that includes lightweight and medium-weight DMM-1 pattern predictors. DFPS starts using the lightweight predictor, whose output is compared with a threshold and then the algorithm employs a DMM-1 refinement or the medium-weight predictor. The result of this last predictor is compared against a new threshold, where the encoder decides if the remaining patterns of the DMM-1 algorithm or only its refinement should be evaluated. Experiments evaluating DFPS encoding efficiency in the all-intra mode demonstrate that by reducing 71% and 84% of the DMM-1 patterns’ evaluation, the complexity is reduced 11.7% and 13.4%, respectively, without significantly affecting the quality of the synthesized views.

DMNI: A specialized network interface for NoC-based MPSoCs

Current proposals of NoC-based MPSoC adopt an NI (Network Interface) interconnected to a DMA (Dir... more Current proposals of NoC-based MPSoC adopt an NI (Network Interface) interconnected to a DMA (Direct Memory Access) module to enable the communication between processors through the NoC. The adoption of both modules decouples computation from communication, and a standard interface at the NI provides an abstract way for designers to connect new cores. However, this architecture is inherited from bus-based architectures and can be optimized, by removing unnecessary interfaces, signals, and registers. This paper presents a specialized communication interface for NoC-based MPSoCs, called DMNI (Direct Memory Network Interface). The DMNI merges the functionalities of the DMA and the NI into a single component, directly connecting the NoC router with the processor memory. To avoid stalls in the communication, the design of the DMNI supports simultaneous packet reception and transmission. A simplified and generic programming interface exposes the DMNI services to the software layer. Results show a reduction in the silicon area and performance improvement in the packet transmission.

Heuristic-Based Fast Multi-type Tree Decision Scheme for Luminance

Springer eBooks, 2022

Conclusions and Open Research Possibilities

Springer eBooks, Aug 21, 2019

This chapter summarizes the conclusions and the contributions described along with this book. It ... more This chapter summarizes the conclusions and the contributions described along with this book. It highlights the importance of reducing the encoding effort of the Three-Dimensional High Efficiency Video Coding (3D-HEVC) depth maps and presents a brief description of the main contributions described throughout the chapters. Besides, this chapter shows and discusses open research possibilities.

Blockchain Applied in Decentralization of Ground Stations to Educational Nanosatellites

Zenodo (CERN European Organization for Nuclear Research), Mar 22, 2023

Space has increasingly attracted the attention of governments, large industries, and universities... more Space has increasingly attracted the attention of governments, large industries, and universities. One of the most popular strategies in recent years has been the adoption of nanosatellites to fulfill different missions, which can work alone or in constellations. Universities stand out among the agents launching nanosatellites, with more than 600 launches until 2022. Given the growth of entities that control space missions, it is necessary to implement new methods for communication between control and satellite to accelerate data transmission and provide a high-security degree. Our work proposes a consortium architecture between Ground Stations (GSs) so that a GS as a Service (GSaaS) works with low cost, reliability, and resource sharing. We simulated a nanosatellite mission in Low Earth Orbit (LEO) with MATLAB to obtain the parameters of average communication time, propagation loss, and at which angles the communication would be most affected by atmospheric phenomena. Then, we implement business rules for communication between GS and satellites using smart contract concepts. We set up a blockchain to provide the decentralization infrastructure and created a web service to provide a communication API between nanosatellite and blockchain. We simulated the firmware update process, showing that the nanosatellite took around 20 minutes to request all 32-byte fragments of 301 Kb firmware. Considering the time interval that the communication window between GS and nanosatellite remains active, the entire firmware transmission takes two to three communication slots. However, the transmission time is drastically reduced in a scenario with two or more GSs. Furthermore, the GSaaS decentralized infrastructure allows the consortium of GSs to communicate agnostically with the satellites, preserving firmware privacy due to the cryptography used in blockchain transactions.

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Fast 3D-Hevc Depth Maps Intra-Frame Prediction Using Data Mining

This paper presents a fast 3D-High Efficiency Video Coding (3D-HEVC) depth maps intra-frame predi... more This paper presents a fast 3D-High Efficiency Video Coding (3D-HEVC) depth maps intra-frame prediction based on static Coding Unit (CU) splitting decisions trees. This coding approach uses data mining to extract the correlation among the encoder context attributes and to define a split decision tree for each CU level of the depth maps encoding. The decision trees were trained using the information extracted from 3D-HEVC Test Model (3D-HTM) and using the Common Test Conditions (CTC). Each decision tree defines if the current CU must be split into smaller sizes, considering the encoding context through the evaluation of some current encoder attributes. The proposed solution reaches a complexity reduction of 59.0% for depth maps coding with a negligible impact of 0.18% in the encoding efficiency of synthesized views.

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Real-time simplified edge detector architecture for 3D-HEVC depth maps coding

This paper introduces the Simplified Edge Detector (SED) architecture for 3D-HEVC depth maps codi... more This paper introduces the Simplified Edge Detector (SED) architecture for 3D-HEVC depth maps coding. The SED algorithm classifies the encoding block as homogeneous or edge. When SED classifies the encoding block as homogeneous, the encoding is simplified skipping the bipartition modes evaluation. This approach is capable of reducing 96.7% the bipartition modes evaluation with a drawback of only 0.94% in BD-rate. The SED hardware is capable of providing the decision for all available blocks inside a 32×32 block in only 34 cycles, with a power dissipation of only 25 μW per frame, when synthesized for 65 nm ST standard cells technology.

Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos

The 3D High Efficiency Video Coding (3D-HEVC) needs specialized tools, such as the Depth Modeling... more The 3D High Efficiency Video Coding (3D-HEVC) needs specialized tools, such as the Depth Modeling Mode (DMM), for dealing with texture and depth map information. This work proposes a low area reconfigurable hardware for sharing a DMM-1 and DMM-4 decoding implementation. When synthesizing for a 65nm ST technology, the designed architecture uses only 5,165 gates and dissipates 1.57 mW, considering the frequency to decode the worst-case scenario. Compared to the state-of-the-art, it is notable that our proposal requires only a few extra hardware to enable a DMM-1 and DMM-4 sharing architecture.

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