Papers by Purandar Bhaduri
Formal specification and verification of hardware designs
Proceedings of SPIE, Sep 1, 1998
Designing modern processors is a great challenges as they involve millions of components. Traditi... more Designing modern processors is a great challenges as they involve millions of components. Traditional techniques of testing and simulation do not suffice as the amount of testing required is quite enormous. Design verification is an effective alternative technique for increasing ...
Design Automation for Embedded Systems, Dec 5, 2019
Real-time safety-critical systems are getting more complicated due to the introduction of mixed-c... more Real-time safety-critical systems are getting more complicated due to the introduction of mixed-criticality systems. The increasing use of mixed-criticality systems has motivated the real-time systems research community to investigate various non-functional aspects of these systems. Energy consumption minimization is one such aspect which is just beginning to be explored. In this paper, we propose a time-triggered dynamic voltage and frequency scaling (DVFS) algorithm for uniprocessor mixed-criticality systems. We show that our algorithm outperforms the predominant existing algorithm which uses DVFS for mixedcriticality systems with respect to minimization of energy consumption. In addition, ours is the first energy-efficient time-triggered algorithm for mixed-criticality systems. We prove an optimality result for the proposed algorithm with respect to energy consumption. Then we extend our algorithm for tasks with dependency constraints. Keywords Real-time systems • Mixed-criticality systems • Energy-efficient computing • Time-triggered scheduling • EDF-VD • TT-Merge B Lalatendu Behera
IEEE Transactions on Mobile Computing, Aug 1, 2015
The IEEE 802.11 standard for wireless local area networks defines a power management algorithm fo... more The IEEE 802.11 standard for wireless local area networks defines a power management algorithm for Independent Basic Service Set (IBSS) allowing it to save critical battery energy in low powered wireless devices. The power management algorithm for IBSS uses beacon intervals (BIs) as the time unit, where every BI consists of an Announcement Traffic Indication Message (ATIM) window and a data window. The stations that have data to send need to go through a handshaking procedure in the ATIM window. If this handshaking is successful, the station remains awake in the data window and participates in the data communication. Otherwise, it goes into the sleep mode. This paper presents an analytical model to compute the throughput, expected delay and expected power consumption in an IEEE 802.11 IBSS in Power Save Mode (PSM) for different traffic conditions in the network. The impact of data arrival rate, network size and size of the BI on the performance of the IEEE 802.11 DCF in PSM is also analyzed. This analysis reveals a clear trade-off among throughput, delay and average power consumption. The trade-off analysis is useful for designing efficient power consumption algorithms while maintaining the consistence performance of the network in terms of throughput and delay.
iitg.ernet.in
Abstract—In the IEEE 802.11 Power Save Mode (PSM) specified for Independent Basic Service Set (IB... more Abstract—In the IEEE 802.11 Power Save Mode (PSM) specified for Independent Basic Service Set (IBSS), time is divided into beacon intervals. At the beginning of each beacon interval, each station in the power save mode periodically wakes up for a duration called ...
Ad Hoc Networks, 2014
The IEEE 802.11 standard defines a power management algorithm for wireless LAN. In the power mana... more The IEEE 802.11 standard defines a power management algorithm for wireless LAN. In the power management for Independent Basic Service Set (IBSS), time is divided into Beacon Intervals (BIs) and each BI is divided into an Announcement Traffic Indication Message (ATIM) window and a data window. The stations that have successfully transmitted an ATIM frame within the ATIM window compete to transmit data frames in the rest of the BI. This paper analyzes the performance of the IEEE 802.11 Power Save Mode (PSM) in single hop ad hoc networks using a discrete-time Markov chain for a data frame transmission together with the corresponding ATIM frame transmission. The paper presents an analytical model to compute the throughput, average delay and power consumption in IEEE 802.11 IBSS in PSM under ideal channel and saturation conditions. The impact of network size on the throughput, delay and power consumption of the IEEE 802.11 DCF in Power Save Mode is also analyzed. This can be used to find an efficient scheme that can maximize the network throughput while saving power consumption for resource constrained ad-hoc wireless networks. The analytical work is validated with simulation results obtained from Qualnet 5.0.1 network simulator.
2013 IEEE Conference on Computer Aided Control System Design (CACSD), 2013
In order to obtain resource efficient implementations of control loops on embedded platforms, rec... more In order to obtain resource efficient implementations of control loops on embedded platforms, recently there has been a renewed interest in studying stability and various other quality-of-control (QoC) metrics in the presence of control message drops. Towards this, different methods have been proposed to quantify the impact of message drops on stability and control performance. In this paper we will survey these techniques and clarify the relationship between them. Given a drop pattern that satisfies stability and specified QoC constraints, it is important to check whether an implementation platform satisfies this pattern. In other words, whether the control loop in question may be implemented on this platform. Given an architecture, we will also show how certain notions of expressing drop patterns are easier to verify compared to others.
Logical Methods in Computer Science
Weighted automata are a generalization of nondeterministic automata that associate a weight drawn... more Weighted automata are a generalization of nondeterministic automata that associate a weight drawn from a semiring $K$ with every transition and every state. Their behaviours can be formalized either as weighted language equivalence or weighted bisimulation. In this paper we explore the properties of weighted automata in the framework of coalgebras over (i) the category $\mathsf{SMod}$ of semimodules over a semiring $K$ and $K$-linear maps, and (ii) the category $\mathsf{Set}$ of sets and maps. We show that the behavioural equivalences defined by the corresponding final coalgebras in these two cases characterize weighted language equivalence and weighted bisimulation, respectively. These results extend earlier work by Bonchi et al. using the category $\mathsf{Vect}$ of vector spaces and linear maps as the underlying model for weighted automata with weights drawn from a field $K$. The key step in our work is generalizing the notions of linear relation and linear bisimulation of Boreal...
2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
Path-based equivalence checkers (PBECs) have been successfully applied for verification of progra... more Path-based equivalence checkers (PBECs) have been successfully applied for verification of programs from diverse domains and at various stages of high-level synthesis. These verifiers can be sound but not complete. Therefore, non-equivalence cases require further investigation of the two programs being compared by some human expert. In this work, we show how a counter-trace (cTrace) can be generated in the case of nonequivalence reported by the PBEC. We show how a Bounded Model Checker (CBMC) can be used to find suitable initialization values for input variables (i.e., a counterexample) for a given cTrace. With our counterexample generation framework, we show how a strong non-equivalence decision can be taken in a PBEC. We also show that some false negative cases of the PBEC can also be revealed using this framework. Experimental results demonstrate the usefulness of our method.
arXiv (Cornell University), Feb 19, 2017
In order to study the axiomatization of the if-then-else construct over possibly non-halting prog... more In order to study the axiomatization of the if-then-else construct over possibly non-halting programs and tests, the notion of C-sets was introduced in the literature by considering the tests from an abstract C-algebra. This paper extends the notion of C-sets to C-monoids which include the composition of programs as well as composition of programs with tests. For the class of C-monoids where the C-algebras are adas a canonical representation in terms of functional C-monoids is obtained.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019
Translation validation is the process of proving that the target code is a correct translation of... more Translation validation is the process of proving that the target code is a correct translation of the source program being compiled. In this work, we propose a translation validation method to verify code motion transformations involving loops applied during the scheduling phase of high-level synthesis (HLS). Our method is capable of ignoring false computations during translation validation. In this work, we show that how to generate a counter-trace (cTrace) using the internal information of verifier in the case of non-equivalence reported by a translation validation method. We also show how a Bounded Model Checker (CBMC) can be used to find a counterexample for a given cTrace. Experimental results demonstrate the usefulness of our method. CCS CONCEPTS • Software and its engineering → Formal software verification.
Categorical logic in models of concurrency
In recent years many competing models of concurrency have been proposed, but a unified theory of ... more In recent years many competing models of concurrency have been proposed, but a unified theory of the semantics of concurrent processes is yet to emerge. The aim of this work is to investigate some of these models from the point of view of categorical logic, specifically the relationship between theories and models. In categorical terms, a theory is a category with certain completeness properties and a model is a functor preserving those properties. We show that the familiar categories of models of concurrency are equivalent to models of geometric theories. We explore the relationship between duality of schedules and automata, geometric logic and categories of embeddings in relating the behavior of a concurrent system with its specification. In the process a degree of uniformity is seen to emerge in the various models.
Timing Analysis of Embedded Systems using Model Checking
Distributed Computing and Internet Technology, 2017
Real-time safety-critical systems are getting more complex by integrating multiple applications w... more Real-time safety-critical systems are getting more complex by integrating multiple applications with different criticality levels on a single platform. The increasing complexity in the design of mixedcriticality real-time systems has motivated researchers to move from uniprocessor to multiprocessor platforms. In this paper, we focus on the time-triggered scheduling of both independent and dependent mixedcriticality jobs on an identical multiprocessor platform. We show that our algorithm is more efficient than the Mixed criticality Priority Improvement (MCPI) algorithm, the only existing such algorithm for a multiprocessor platform.
Algebra universalis, 2020
This paper introduces the notions of atoms and atomicity in Calgebras and obtains a characterisat... more This paper introduces the notions of atoms and atomicity in Calgebras and obtains a characterisation of atoms in the C-algebra of transformations. Further, this work presents some necessary conditions and sufficient conditions for the atomicity of C-algebras and shows that the class of finite atomic C-algebras is precisely that of finite adas. This paper also uses the if-then-else action to study the structure of C-algebras and classify the elements of the C-algebra of transformations.
Algebra universalis, 2018
In order to study the axiomatization of the if-then-else construct over possibly non-halting prog... more In order to study the axiomatization of the if-then-else construct over possibly non-halting programs and tests, the notion of C-sets was introduced in the literature by considering the tests from an abstract C-algebra. This paper extends the notion of C-sets to C-monoids which include the composition of programs as well as composition of programs with tests. For the class of C-monoids where the C-algebras are adas a canonical representation in terms of functional C-monoids is obtained.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
Translation validation is the process of proving that the target code is a correct translation of... more Translation validation is the process of proving that the target code is a correct translation of the source program being compiled. In this work we propose a translation validation method to verify code motion transformations involving loops applied during the scheduling phase of high-level synthesis (HLS). Our method is capable of ignoring false computations during translation validation. We have also identified a scenario involving code motion across loops where the state-of-the-art translation validation method gives false positive results. Our method can prove the non-equivalence of the concerned finite state machines with data paths (FSMDs) in this scenario. We detected a bug in the HLS tool SPARK involving loop invariant code motion using our method. Experimental results demonstrate the usefulness of our method.
A Counter-Example Generation Procedure for Path based Equivalence
IET Software, 2018
Path-based equivalence checkers (PBECs) have been successfully applied for verification of progra... more Path-based equivalence checkers (PBECs) have been successfully applied for verification of programmes from diverse domains and from various stages of high-level synthesis. In the case of non-equivalence, PBEC provides very little information which is not sufficient for further investigation of the two programmes being compared by some human expert. In this work, the authors show how a counter-trace (cTrace) can be generated in the case of non-equivalence reported by the PBEC. Using this cTrace, they also present a procedure to find suitable initialisation values for input variables which reveal the non-equivalence (i.e. counter-example) by using off-the-shelf satisfiability modulo theories (SMT) solvers. To aid the human expert, they also show that how they can visualise this cTrace in the control and data-flow graph of the programmes using the graph visualisation software – Graphviz. This counter-example and visual representation of the corresponding cTrace will be helpful in debugging the root cause of the non-equivalence. The experimental results are encouraging.
ACM Transactions on Design Automation of Electronic Systems, 2017
Real-time and embedded systems are moving from the traditional design paradigm to integration of ... more Real-time and embedded systems are moving from the traditional design paradigm to integration of multiple functionalities onto a single computing platform. Some of the functionalities are safety critical and subject to certification. The rest of the functionalities are nonsafety critical and do not need to be certified. Designing efficient scheduling algorithms which can be used to meet the certification requirement is challenging. Our research considers the time-triggered approach to scheduling of mixed-criticality jobs with two criticality levels. The first proposed algorithm for the time-triggered approach is based on the OCBP scheduling algorithm which finds a fixed-priority order of jobs. Based on this priority order, the existing algorithm constructs two scheduling tables S LO oc and S HI oc . The scheduler uses these tables to find a scheduling strategy. Another time-triggered algorithm called MCEDF was proposed as an improvement over the OCBP-based algorithm. Here we propose...
International Journal of Algebra and Computation, 2017
In order to study the axiomatization of the if-then-else construct over possibly non-halting prog... more In order to study the axiomatization of the if-then-else construct over possibly non-halting programs and tests, this paper introduces the notion of [Formula: see text]-sets by considering the tests from an abstract [Formula: see text]-algebra. When the [Formula: see text]-algebra is an ada, the axiomatization is shown to be complete by obtaining a subdirect representation of [Formula: see text]-sets. Further, this paper considers the equality test with the if-then-else construct and gives a complete axiomatization through the notion of agreeable [Formula: see text]-sets.
2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications, 2015
In this paper we consider the case of a network of Electronic Control Units (ECUs) connected thro... more In this paper we consider the case of a network of Electronic Control Units (ECUs) connected through a FlexRay bus in the automotive domain. Multiple distributed applications can run on this underlying architecture, each partitioned into tasks that are mapped on different ECUs. These applications can often be executed in different functional modes with different requirements on the communication resources in terms of data size and sampling period. Moreover, new applications can be deployed on to the ECUs at run-time. To efficiently utilize the communication resources and accommodate new applications, a certain flexibility in reallocation of the resource is necessary. However, the FlexRay bus requires static configuration of schedules and data mapping in order to guarantee a more deterministic system behavior, allowing little room for flexibility. In order to address this problem, we propose a reconfigurable communication middleware that lies between the application layer and the communication controller layer, which maps messages onto FlexRay schedules, and can be reconfigured at runtime. The configuration is synthesized and deployed online, allowing a certain reallocation of communication resources to applications. In this paper, we describe the design of such a reconfigurable communication middleware and demonstrate its function with an implementation using industry-strength FlexRay design tools.
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Papers by Purandar Bhaduri