Real time and Embedded Systems

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Real-time and embedded systems refer to computer systems designed to perform dedicated functions within strict timing constraints. These systems integrate hardware and software to process data and respond to inputs in real-time, ensuring reliability and efficiency in applications such as automation, control systems, and consumer electronics.

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1. How can scheduling and resource management models be optimized for reliability and real-time constraints in embedded systems?

This area investigates scheduling algorithms and resource management approaches tailored to real-time embedded systems, emphasizing predictability, low overhead, and reliability under hard and soft timing constraints. It is critical because embedded systems often operate within tight deadlines affecting safety and performance, necessitating advanced scheduling techniques that ensure tasks meet deadlines while managing limited resources effectively.

A time-driven scheduling model for real-time operating systems

by Hideyuki Tokuda

2015, Proceedings of the 6th IEEE Real- …

Key finding: This paper identifies limitations of classical scheduling algorithms (fixed priority, FIFO, round robin) in handling dynamic arrivals and stochastic processing times of real-time processes. It advocates for dynamic... Read more

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Race-to-halt energy saving strategies

by Muhammad irfan Awan

2024, Journal of Systems Architecture

Key finding: The study introduces leakage-aware scheduling algorithms based on the race-to-halt strategy, which runs embedded real-time systems at top speed to create idle intervals suitable for deploying low-power sleep states, thereby... Read more

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On the schedulability of a data-centric real-time distribution middleware

by Hector Alexander Mendoza perez

2023, Computer Standards & Interfaces

Key finding: This work analyzes how DDS (Data Distribution Service) supports real-time behavior by integrating real-time concepts such as end-to-end flows from MARTE and applying schedulability analysis, showing that DDS mechanisms can be... Read more

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Using Windows NT for real-time applications: experimental observations and recommendations

by Chia Shen

2025, Proceedings. Fourth IEEE Real-Time Technology and Applications Symposium (Cat. No.98TB100245)

Key finding: Through a systematic experimental evaluation, the paper elucidates Windows NT's limitations for hard real-time applications due to unpredictable delays but suggests that soft real-time tasks with relaxed timing requirements... Read more

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A hierarchical framework for component-based real-time systems

by Giacomo Guidi

2021, Component-Based Software …

Key finding: This paper proposes a two-level scheduling hierarchy for complex real-time embedded applications composed of multiple multi-threaded processes (applications), each capable of specifying its own local scheduler (e.g., FIFO,... Read more

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2. How can component-oriented and model-driven methodologies improve design, verification, and validation of embedded real-time systems?

This thematic area focuses on leveraging component-based design, UML modeling, synchronous programming languages, and model-driven engineering (MDE) to enable early detection of design errors, formal verification, automatic RTOS generation, and separation of concerns, particularly non-functional requirements. These approaches are crucial for managing complexity, improving software quality, and ensuring that timing constraints are met before implementation.

Support for early verification of embedded real-time systems through UML models simulation

by luis ceron

2023

Key finding: The study presents FUMBeS, a framework capable of simulating functional behavior specified in UML models during early design phases, prior to implementation, facilitating early detection of errors and reducing repair costs.... Read more

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Towards validated real-time software

by V. Bertin

2024, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000

Key finding: This paper introduces the TAXYS tool, integrating synchronous programming language ESTEREL with timed-automata-based model checking to automatically generate executable real-time code and its formal timed model, enabling... Read more

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Automatic Generation of a Real-Time Operating System for Embedded Systems

by Alberto Sangiovanni Vincentelli

2022

Key finding: The work proposes an approach where RTOS code is automatically generated from a high-level description using Codesign Finite State Machines (CFSMs), combining hardware and software components co-design. This method improves... Read more

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Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems

by Fabiano Lacerda Carvalho

2024, IFIP – The International Federation for Information Processing

Key finding: This research adapts the FRIDA method to the distributed real-time embedded (DRE) domain to separate and express non-functional requirements (particularly real-time constraints) as aspects early in the requirements analysis... Read more

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metro II

by Alberto Sangiovanni Vincentelli

2022, ACM Transactions on Embedded Computing Systems

Key finding: The metro II environment applies Platform-Based Design (PBD) and metamodeling frameworks to model and simulate heterogeneous cyber-physical systems at multiple abstraction levels, supporting functional and architectural... Read more

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3. What are the practical challenges and solutions for integration and security in real-time embedded and cyber-physical systems?

This area explores integration challenges of embedded real-time systems including virtualization on multicore platforms, secure interfacing of external devices with in-vehicle networks, energy and power constraints in embedded contexts, as well as the use of mobile sensing for monitoring. Solutions encompass real-time aware VM scheduling, authentication protocols for connected vehicles, energy-saving scheduling strategies, and innovative sensor deployments—all ensuring performance, safety, and resource efficiency in complex real-time environments.

Real-time multi-core virtual machine scheduling in xen

by Linh Phan

2023, Proceedings of the 14th International Conference on Embedded Software

Key finding: The authors design and implement RT-Xen 2.0, a real-time VM scheduling framework for Xen hypervisor on multicore platforms that supports global and partitioned schedulers with dynamic/static priorities and periodic/deferrable... Read more

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On authentication in a connected vehicle: Secure integration of mobile devices with vehicular networks

by Kyusuk Han

2023, Proceedings of the Acm Ieee 4th International Conference on Cyber Physical Systems

Key finding: This paper proposes a three-step mutual authentication protocol for integrating mobile devices with in-vehicle networks via a gateway, mitigating security risks introduced by exposing the originally closed CAN bus to external... Read more

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Real Time Operating System Options in Connected Embedded Equipment for Distributed Data Acquisition

by Radu Arsinte

2022, Carpathian Journal of Electronic and Computer Engineering

Key finding: The paper evaluates various portable real-time operating systems for embedded Raspberry Pi devices, aiming to find minimal, flexible, modular, and maintainable RTOS configurations for applications such as environmental... Read more

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Mapping hidden water pipelines using a mobile sensor droplet

by Tiffany Chen

2022, ACM Transactions on Sensor Networks

Key finding: This work introduces PipeProbe, a novel mobile sensor system where a wireless, battery-powered sensor capsule is passively carried by water flow through hidden pipelines, collecting pressure and angular velocity data to infer... Read more

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A Study of Real-Time Embedded Software Systems and Real-time Operating Systems

by sudhir ingole

2016

Key finding: This study surveys characteristics of real-time and embedded systems, emphasizing the criticality of timing constraints and resource limitations. It highlights embedded systems' heterogeneity and the challenging integration... Read more

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All papers in Real time and Embedded Systems

Using GQM for Testing Design Patterns in Real-Time and Embedded Systems on a Software Production Line

by Denis Montini and

2009

University. This PA was used to eliminate systematic error cases listed in a Technical Report (TR) generated by CAR. An information system model was created to allow the elimination of defects, errors, and failures in a design pattern... more

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Improved task management techniques for enforcing EDF scheduling on recurring tasks

by Michael Short

2010, 2010 16th IEEE Real-Time and Embedded Technology …

Abstract The management of tasks is an essential requirement in most real-time and embedded systems, but invariably leads to unwanted CPU overheads. This paper is concerned with task management in real-time and embedded systems employing... more

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Program Instrumentation and Run-Time Analysis of Scoped Memory in Java

by Hichem Zorgati

2005, Electronic Notes in Theoretical Computer Science

We present a method to analyze, monitor and control dynamic memory allocation in Java. It first consists in performing pointer and escape analysis to detect memory scopes. This information is used to automatically instrument Java programs... more

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Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip

by Steven Freear

2000, IEEE Transactions on Parallel and Distributed Systems

This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact mechanics. There are two main significances in this paper.... more

FPUs are shared when they are available for access by more than one processor. FPUs can be made shareable by simply connecting them to multiple NiosII processors’ master ports in the connection matrix of SOPC Builder [12] and then an Avalon arbiter will be automatically built to route the signals. Nevertheless, in general, Altera’s NiosII design environment does not natively support sharing non-memory peripherals between multiple processors

Fig. 11. FPGA architecture of the Fastsim part.

Fig. 12. Objective equations, the correspondent FPU tasks, proces- sor tasks and combined processor tasks.

Fig. 2. Contact area and Fastsim calculation (contact semi-axes a and b have been achieved by Hertz; mo=10, no=10; segments are indexed by i,j (=O, 1, ..., Mo-1; j=0, 1, ..., M0-1) )

Fig. 3. Original contact laws flow chart. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publicatio1 SEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS It is obvious that the greater mo and no in (8) then th calculated creep forces would more closely approximat the continuous form of the contact laws as in (19)

Fig. 4. Restructured contact laws flow chart

Fig. 5. Processor configuration in the Hertz part. arithmetic logic unit is implemented for the fixed-point divide operation as this is required in a small portion in the calculation of the Hertz algorithms. The processor commands its slaves or peripherals via the Avalon bus [11].

Fig. 6. FPGA architecture of the Hertz part. cores used in the design. They are all 3-stage-pipelined and have higher throughput for subsequent operations. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publicatiot E TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS

Fig. 8. (a) Optimal schedule (shortest run time); (b) Another sched- ule (longer run time); (c) Another schedule (even longer run time) task has finished. A stall period will be added if the proc- essor needs to wait for FPU results after the preparation. An IOWR operation approximately takes 21 cycles, and an IORD operation 15 cycles in the case without stall. Note that intermedia variables ‘x_1’, ‘x_2’ and ‘x_3’ are introduced. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publicatio1 {-EE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS

Times) [6] is used as it is one of the simplest DAG sched- uling algorithms and it has been shown to produce good quality results when the communication costs of the edges are ignored [7]. In HLFET, the length of a directed path is defined to be the sum of the weights of all nodes along the path including the initial and final nodes. The level of an exit node is the weight of itself and the level of a non-exit node is defined to be the length of the longest path from that node to the exit node. The HLFET algo- rithm calculates each node’s level which is the same as the node’s priority, according to which the algorithm then schedules the nodes on the list one by one.

The execution of the scheduled tasks of the design, de- rived from Modelsim simulation results, is depicted in Y NOF with token-ring topology works. The 5 processors are assumed to start running simultaneously. In doing a task, a processor needs to acquire a specific token from the previous processor before accessing (write/read) the re- quired FPU, and passes the token to the next processor after FPU accessing, which is denoted by the solid ar- rowed lines in the figure (denoted only for tasks 1w in the figure). The FPU tokens are initialized at TF1 (the FIFO between the processor CPU1 and processor CPU5 as shown in Fig. 11), which allows CPU1 firstly to acquire the token and access the correspondent FPU, followed by CPU2, CPU3, CPU4 and CPU5. Note that the execution at the token FIFO side is not shown in the figure. Secondly, Fig. 13(a) also illustrates the interaction between the hardware and software. In each operation for the hard- ware multiply, divide and square-root FPUs, the two sets of operands are distributed to the two duplicate FPUs of the same type by the programmed software, so that the two calculations can be processed in parallel. The dotted arrowed lines in Fig. 13(a) denote such operation for proc- essor tasks 2w and 2r on CPU1. Thirdly, a processor wil stall if the token is not available for it to read or if FPU results are pending. The initial stalls (IS) are inevitably produced due to the token-ring feature. They are of fixed duration and are ignorable if considered in a long execu- tion procedure. The subsequent stalls (SS) are produced due to the overly long latency of the FPUs. Both types of stall can postpone the overall complete time. The delay is accumulated from preceded processors’ stalls and previ- Fig. 13. (a) Task execution in the final design. (b) Task execution in another design with less FPUs The 5 processors CPU1-CPU5 are programmed with code prior to run time. The scheduling of the code has been previously optimized for the target algorithm. The NiosII’s hardware abstraction layer (HAL) single- threaded runtime environment is employed rather than using an operating system as it reduces the overall pro- gram size and running time.

Fig. 16. Experiment and validation flow. tacts’ calculation per iteration, which approximately agrees with the theoretical value (37050 cycles) stated in section 3.3. In step 4, the single-precision results are downloaded from the SDRAM and converted to double- precision format. In the final step, these results are com- pared with the previously recorded output data from the contact laws model in Simulink. The longitudinal and lateral contact force of the FPGA results on one of the con- tacts and the relative errors of the comparison are shown in Fig. 17 and Fig. 18, for the curved track’s experiment

Fig. 17. FPGA calculation results and errors (on curved track)

and for the irregularized straight track’s experiment re- spectively. Both of the relative errors in percentage are within the order of 10” which is very small considering that the Fastsim algorithm itself contains a 10%-15% rela- tive error based on the comparison with the exact theory \uthorized licensed use limited to: University of Leeds. Downloaded on September 2, 2009 at 09:41 from IEEE Xplore. Restrictions apply

Fig. 18. FPGA calculation results and errors (on irregularized straight track)

Authorized licensed use limited to: University of Leeds. Downloaded on September 2, 2009 at 09:41 from IEEE Xplore. Restrictions apply.

thesizing the design with Quartus 7.1 into the targeted device. With more data cache embedded, CPU0 consumes more on-chip memory than CPU1~CPU5 do, and also takes more LEs due to its additional built-in JTAG mod- ule and fixed-point divide unit. Each type of FPUs for the Fastsim utilizes more Logic Elements than that for the Hertz, as a result of their higher complexity with the buff- ering FIFOs. All buffering FIFOs are implemented with on-chip RAM, except that in the Square-root FPU which is implemented by LEs, because of on-chip RAM insuffi- ciency on the device. The token FIFOs use LEs as well. The implementation of the dual-port memory consumes on-chip RAM and a few LEs. ‘Others’, including a Ether- net controller, a SDRAM controller and other miscellane- ous connections, consumes 11.8% of total LE. All on-chip RAM are used. The statistics also shows that the design has a good capability to balance the usage between on- chip RAM and LE. Frequency 60 MHz is achieved on this device.

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Using Intelligent Digital Cameras to Monitor Aerodrome Surface Traffic

by Nikolaos Grammalidis

2005, IEEE Intelligent Systems

Figure 1. The Intervuse system architecture. (Asterix is a standard for exchanging radar data.) which correspond to binary output. The air- craft then indicates its presence by activat- ing these detectors. Activated detectors appear in bright green on the system display (shown in light gray in figure 3); deactivated detectors are black. We can configure up to 32 virtual detectors per camera, and we can define more complex virtual detectors by combining detector outputs using logical and mathematical expressions (such as AND, Once we’ ve selected the virtual detectors’ location, the MVP can estimate the back- ground (that is, the color values of pixels within the virtual detectors) in the absence of a vehicle. Virtual detectors then detect a We can define rectangular areas, called virtual detectors, on the camera image plane,

Figure 3. A camera’s field of view and detector configuration. The aircraft indicates its presence by activating detectors, which then appear bright green on the system display (shown in light gray here).

Figure 4. A traffic-situation display for Germany's Mannheim Airport.

For more information on this or any other com- puting topic, please visit our Digital Library at www.computer.org/publications/dlib.

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Implementing fault-tolerance in real-time programs by automatic program transformations

by Tolga Ayav

2008

We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial fault-intolerant system consists of a set of independent periodic tasks scheduled onto a set of fail-silent processors connected by a... more

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Implementing Fault-Tolerance in Real-Time Systems by Program Transformations

by Tolga Ayav

2007

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Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

by Ivan Gonzalez

2007, IEEE Micro

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Mitigating soft error failures for multimedia applications by selective data protection

by Nalini Venkatasubramanian

2006, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06

With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft errors. Although Error Correction Code based mechanisms... more

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An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation

by Jung-Yup Kang

2008, IEEE Transactions on Computers

In general, the main purpose of using Processor-in-Memory (PIM) modules is to dramatically increase the Data-Level Parallelism (DLP) and avoid the limited issue rate of current systems (even when they include SIMD extensions) caused by... more

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A methodology for mapping sysML activity diagram to time Petri net for requirement validation of embedded real-time systems with energy constraints

by Gustavo Callou

2009

In this paper we use the Activity diagram of the System Modeling Language (SysML) in combination with the new UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) in order to validate functional, timing and low... more

For this example the stereotype (ResourceUsage) and tag- ged values (execTime and energy) were used. The stere- otype describes an action. Tagged values consist of a pro- perty name and an assigned value. For this example, the ResourceUsage stereotype describes, respectively, the de- lay and the energy consum ption of the activity A, in this case, 10 seconds and 20 joules. The tagged values are {duration = (10,’ s’)} and {energy = (20,'7’)}. More information about all stereotypes and tagged values suppor- ted by MARTE can be found in [1].

3 (a)) are assigned with the interval (thin interval), respec- tively, [35,35] and [20,20], since that the state space [3] is considerably smaller than if only one PN-transition with the interval equal to [35,20] was adopted. Hence, this model al- lows a faster reachability graph path search. The in_A place represents the activity A entry as well as the choice point between the worst and best related to the execution time and energy consumption of the activity A. The others places (W.A, B_A and out_A) represent, respectively, the worst case state, the best case state and the activity A exit. 4.3. Mapping Transitions

A final state represents the respective final state in SysML-AD. This final state is mapped into a place in ETPN model (Figure 5 (b)), such that the presence of a token in the endSta_A place represents the end of the SysML-AD. Mo- reover, the t_end_A PN-transition is used to represent the AD-transition between the activity A and the final state.

A diamond with one flow entering and several leaving. The flows leaving include conditions although some mode- lers will not indicate the conditions if it is obvious. In the mapping process, the t_in_deci PN-transition represents the entry on the decision and the places brc_B represents the decision point.

ble to dispatch pulse streams to the leds in order to gene- rate a pulse frequency. This process has requirement cons- traints (execution time and energy consumption). The time and energy consumption intervals’ values in which entire activities must be executed are, respectively, [35, 40] us and [2170, 2320] 7J [6]. It is important to highlight that these constraints are deeply related to the hardware plat- form (Philips LPC2106 processor, an 32-bit microcontroler with ARM7 core). Figure 9. Activity diagram of excitation pro- cess with time and energy constraints.

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Shortest-path algorithms for real-time scheduling of FIFO tasks with minimal energy use

by Bruno Gaujal

2005, ACM Transactions on Embedded Computing Systems

We present an algorithm for scheduling a set of non-recurrent tasks (or jobs) with FIFO realtime constraints so as to minimize the total energy consumed when the tasks are performed on a dynamically variable voltage processor. Our... more

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A Model-Driven Design Framework for Massively Parallel Embedded Systems

by jean-luc Dekeyser and

2011, ACM Transactions on Embedded Computing Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded... more

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Mitigating soft error failures for multimedia applications by selective data protection

by Aviral Shrivastava

2006

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Energy-efficient, utility accrual scheduling under resource constraints for mobile embedded systems

by E. Douglas Jensen

2006, ACM Transactions on Embedded Computing Systems

We present an energy-efficient, utility accrual, real-time scheduling algorithm called ReUA. ReUA considers an application model where activities are subject to time/utility function time constraints, mutual exclusion constraints on... more

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Bodyqos: Adaptive and radio-agnostic qos for body sensor networks

by John Stankovic

2008

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High Robustness Requirements in a Common Criteria Protection Profile

by thuy dung Nguyen

2006

The development of a Common Criteria protection profile for high-robustness separation kernels requires explicit modifications of several Common Criteria requirements as well as extrapolation from existing (e.g., medium robustness)... more

functional requirements are levied only on the TSF while the security assurance requirements are imposed on the entire TOE. The following sections discuss the security requirements included in the current SKPP working draft, which is based on CC Version 2.2. 4.1. Security functional requirements

Figure 2. Security functional requirements in SKPP Similarly, it is important to levy both functional and assurance requirements on the configuration data The last extended security functional requirement belongs to a new family in the Resource Utilization class. This requirement addresses the objective that the TSF exhibits predictable utilization of both time and space resources.

Table 1. Authorization Matrix for the Least Privilege Abstraction [1]

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Work in progress - multi-disciplinary real-time and embedded systems laboratory and course sequence

by James Vallino

2004, 34th Annual Frontiers in Education, 2004. FIE 2004.

Small electronic products for the mass market are increasingly incorporating programmable components. The software in these devices has constraints that are markedly different from software designed for a generalpurpose computer. Most... more

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Compositional Dependability Evaluation for STATEMATE

by Ralf Wimmer

2000, IEEE Transactions on Software Engineering

Software and system dependability is getting ever more important in embedded system design. Current industrial practice of model-based analysis is supported by state-transition diagrammatic notations such as Statecharts. State-of-the-art... more

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Characterizing and modeling user activity on smartphones: summary

by Gokhan Memik

2010

In this paper, we present a comprehensive analysis of real smartphone usage during a 6-month study of real user activity on the Android G1 smartphone. Our goal is to study the high-level characteristics of smartphone usage, and to... more

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Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

by Sana Cherif

2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. However due to the tremendous amount of hardware... more

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Modeling Timing Requirements in Problem Frames Using CCSL

by Frederic Mallet

As the embedded systems are becoming more and more complex, requirements engineering approaches are needed for modeling requirements, especially the timing requirements. Among various requirements engineering approaches, the Problem... more

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A Model-Driven Design Framework for Massively Parallel Embedded Systems

by Anne Etien

2011, ACM Transactions on Embedded Computing Systems

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Achieving Real-Time Target Tracking Using Wireless Sensor Networks1

by Tarek Abdelzaher

2006, Real-Time and …

Target tracking systems, consisting of thousands of low-cost sensor nodes, have been used in many application domains such as battlefield surveillance, wildlife monitoring and border security. These applications need to meet certain... more

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Design and performance evaluation of an adaptive FPGA for network applications

by Christoforos Kachris

2009, Microelectronics Journal

In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses... more

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Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

by Ivan González

2007, IEEE Micro

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Software Real-Time Resource Modeling

by Jerome Delatour

2008, Lecture Notes in Electrical Engineering

Figure 5 illustrates the use of an AssociationClass to describe interactions among concurrent resources. Since the “InteractionResource” stereotype extends the UML Classifier metaclass, an UML AssocationClass may be stereotyped as any InteractionResource substereotype e.g. “NotificationResource”, “MessageComResource”, and “MutualExclusionResource”). In this example, the execution support provides concurrency resources “Alarm” and “Task”) to compute instructions. These resources are described as UML classes and respectively stereotyped as “Alarm” and “SchedulableRessource”. In this example, an “Alarm” resource may interact with a

Figure 6 describes a “taskSpawn()” service as both task creating and task activating. In the same way, to activate a task, the user can either call the “taskSpawn()” or the “taskA ctivate()” service. This also allows users to express the same semantics for multiple features through use of the same tag (see priorityElements in figure 6). Figure 6 - Examples of tagged values

“trajectoryControl” operation body is the code which has to be executed in the context of that schedulable resource.

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Towards a Framework for Explicit Platform-Based Transformations

by Jerome Delatour

2008, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC)

One promising solution for meeting the demands of constantly-evolving Real-Time Embedded (RTE) software is the model-driven development (MDD) paradigm, based on the principle of separating the description of an application from its... more

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Interdisciplinary Teaming as an Effective Method to Teach Real-Time and Embedded Systems Courses

by James Vallino

2008, … the 2008 Workshop on Embedded Systems …

The body of knowledge for engineering real-time and embedded systems spans multiple computing disciplines. To effectively prepare students to work in these areas requires coursework that uses an interdisciplinary approach. This paper... more

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Polychronous Analysis of Timing Constraints in UML MARTE

by Thierry Gautier

2010, 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification... more

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Using Intelligent Digital Cameras to Monitor Aerodrome Surface Traffic

by Enrico Piazza

2005, IEEE Intelligent Systems

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An efficient modeling and execution framework for complex systems development

by C. Mraidha

2011

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An efficient modeling and execution framework for complex systems development

by Manal Filali

2011

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Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

by Jean-luc Dekeyser

2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Mitigating soft error failures for multimedia applications by selective data protection

by Aviral Shrivastava

2006, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06

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A methodology for mapping sysml activity diagram to time petri net for requirement validation of embedded real-time systems with energy constraints

by Bruno Nogueira

2009

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Clock constraint specification language: specifying clock constraints with UML/MARTE

by Frederic Mallet

2008

The OMG UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) aims at using the general-purpose modeling language UML in the domain of Real-Time and Embedded (RTE) systems. To achieve this goal, it is absolutely... more

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Analysis and Experimentation of a 4-DOF Haptic Device

by Shahram Payandeh

2008, 2008 Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems

This paper presents a new configuration of a haptic device based on a 4-DOF hybrid spherical geometry. The Spherical Parallel Ball Support (SPBS) type device, as it is referred to, consists of a particular design with the intersecting... more

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A Decision-Theoretic Planner with Dynamic Component Reconfiguration for Distributed Real-Time Applications

by ANKIT GUPTA

2007

Distributed real-time embedded (DRE) systems often perform sequences of coordination and heterogeneous data manipulation tasks to meet specified goals. Autonomous operation of DRE systems in dynamic environments can benefit from the... more

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Systematic dynamic memory management design methodology for reduced memory footprint

by Dimitrios Soudris

2006, ACM Transactions on Design Automation of Electronic Systems

New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they must heavily rely on Dynamic Memory (DM) due to the unpredictability of the input data... more

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QoS-UniFrame: A Petri Net-Based Modeling Approach to Assure QoS Requirements of Distributed Real-Time and Embedded Systems

by Mikhail Auguston

2005

Assuring quality of service (QoS) requirements is critical when assembling a distributed real-time and embedded (DRE) system from a repository of existing components. This paper presents a two-level approach for assuring satisfaction of... more

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MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

by jean-luc Dekeyser

2008, 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel... more

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Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

by jean-luc Dekeyser and

2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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thereal Network on Chip: Concepts, Architectures, and Implementations

by Andrei Radulescu

2005, IEEE Design & Test of Computers

IN CUTTING-EDGE and future technologies, circuit designs are projected to witness a large degree of variation that will affect their behavioral characteristics. These include perturbations in the manufacturing process that can cause a... more

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Analysis and Experimentation of a 4DOF Haptic Device

by Andy Ma

2008

This paper presents a new configuration of a haptic device based on a 4-DOF hybrid spherical geometry. The spherical parallel ball support (SPBS) type device, as it is referred to, consists of a particular design with the intersecting... more

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QoSPL: A QoS-Driven Software Product Line Engineering Framework for Distributed Real-time and Embedded Systems

by Mihran Tuceryan and

2006, Proc. 18th Intl. Conf. Software Engineering and Knowledge Engineering

The current synergy of Component-Based Software Engineering (CBSE) and Software Product Line Engineering (SPLE) requires evolution to facilitate Distributed Realtime and Embedded (DRE) system construction. Such evolution is driven by... more

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Specification and management of QoS in real-time databases supporting imprecise computations

by Jörgen Hansson

2000, IEEE Transactions on Computers

Real-time applications such as e-commerce, flight control, chemical and nuclear control, and telecommunication are becoming increasingly sophisticated in their data needs, resulting in greater demands for real-time data services that are... more

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ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks

by Jörgen Hansson

2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007)

We have developed an analysis-based design tool, ANDES, for modeling a wireless sensor network system and analyzing its performance before deployment. ANDES enables designers to systematically develop a model for the system, refine it... more

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Proving properties of real-time systems through logical specifications and Petri net models

by Dino Mandrioli

1994, IEEE Transactions on Software Engineering

The problem of formally analyzing properties of real-time systems is addressed. A method is proposed that allows specifying system properties in the TRIO language (an extension of temporal logic suitable to deal explicitly with the "time"... more

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Real time and Embedded Systems

Key research themes

1. How can scheduling and resource management models be optimized for reliability and real-time constraints in embedded systems?

2. How can component-oriented and model-driven methodologies improve design, verification, and validation of embedded real-time systems?

3. What are the practical challenges and solutions for integration and security in real-time embedded and cyber-physical systems?

Related Topics

All papers in Real time and Embedded Systems