Polychronous Analysis of Timing Constraints in UML MARTE

2008

The UML Prole for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and oers a broad range of capabilities required to model RTE systems including both discrete/dense and chronometric/logical time. MARTE OMG specication introduces a Time Structure inspired from Time models of the concurrency theory and proposes a new clock constraint specication language (CCSL) to specify, within the context of UML, usual logical and chronometric time constraints. This paper presents, for the rst time, the formal semantics of some representative CCSL clock constraints concerning logical discrete-time. Considering the Time Structure as a concurrent system, we propose a dynamic interpretation to build acceptable solutions that fully respect the constraints. An unusual example about processing Easter days illustrates the use of CCSL and the construction of solutions.

2000

ABSTRACT: Design of real-time embedded,systems requires particular attention to the careful scheduling of application onto execution platform. Precise cycle allocation is often requested to obtain full communication,and computation throughput. Our objective is to provide a UML prole where events, actions, and objects can be annotated by ìlogicalî clocks. Initially, clocks are not necessarily related. The goal of the scheduling process

Proceedings of the 29th Annual ACM Symposium on Applied Computing, 2014

Analysis of timing constraints is an essential part in developing real-time embedded software. Performing the timing analysis during the early development phases prevents timing violations and enhances software quality. In the development of real-time embedded software, UML timing diagrams can play a significant role since they can provide not only intuitive specifications for timing constraints, but also valuable information for verifying system requirements. However, as software complexity increases, modeling timing diagrams is becoming difficult and costly. We propose an automated construction approach of timing diagrams from UML sequence diagrams and state machine diagrams with MARTE annotations. The proposed approach enables developers of RTES to save time required for modeling timing diagrams and prevents making mistakes in construction of timing diagrams.

2007

Time and timing features are an important aspect of modern electronic systems, often of embedded nature. We argue here that in early design phases, time is often of logical (rather than physical) nature, even possibly multiform. The compilation/synthesis of heterogeneous applications onto heterogeneous architecture platforms then largely amounts to adjusting the former logical time(s) demands onto the latter physical time abilities. Many distributed scheduling techniques pertain to this approach of "time refinement". We provide an extensive Time metamodel that opens the possibility to cast this approach in a Model-Driven Engineering light. Then, meaningful transformations can extend allocation, as defined in SysML, to timed models. Time modeling also allows for a precise description, in a OCL-like fashion, of timed properties of events and clocks (periodic, sporadic, bounded jitter,...). Finally, Time can be interpreted to control the system dynamics, unlike other proposals based on uninterpreted stereotype annotations. This report starts with a presentation of the "Time" and "Allocation" sub-profiles of the UML profile for Marte. Their use is illustrated on a communication example borrowed from the AADL standard. This study highlights semantic variations between immediate and delayed communications, and provides a generalization.

2012 IEEE Sixth International Conference on Software Security and Reliability, 2012

The UML has been used to describe structures and behaviors of time-triggered embedded software. Analysis of timing constraints is an important issue in developing time-triggered embedded software. Among multiple types of UML diagrams, timing diagrams are appropriate to show state changes and their relevant events of objects over time with timing constraints. However, there has been little study on how to specify and utilize timing diagrams in practice. Given sequence diagrams and state machine diagrams with MARTE annotations, we propose a systematic way to construct timing diagrams with MARTE annotations. To get well-formed models, we check timing constraints and consistency of the input UML/MARTE models. We present checking criteria for wellformed UML/MARTE models and systematic transformation rules. To show effectiveness of our approach, we demonstrate an illustrative example of GCU (Guidance and Control Unit) software used in avionics systems.

Proceedings of the 2014 IEEE 15th International Conference on Information Reuse and Integration (IEEE IRI 2014), 2014

UML and MARTE are standardized modeling languages widely used in industry for the design of realtime systems. However, formal verification at early phases of the system lifecycle for UML/MARTE models remains an open issue mainly for dependability features. In this paper, we show how we can provide a formal verification of time properties from a UML/MARTE description. For this, we translate this latter description expressed (Timed Computation Tree Logic). We illustrate the proposed approach on a case study derived from a real-time asynchronous system (Integrated Modular Avionics (IMA)-based airborne system).

Dependability is a key feature of critical Real-Time Systems (RTS). In fact, errors may lead to disastrous consequences on life beings and economy. To ensure the absence or avoidance of such errors, it is important to focus on RTS veri�cation as early as possible. As MARTE UML pro�le is the standard de facto for modelling RTS, we suggest to ex- tend UML diagrams by a formal veri�cation stage. More precisely, in the �rst part we propose a transformation approach of Interaction Overview Diagrams and Timing Diagram merged with UML-MARTE annotations into Time Petri Nets (TPN) models Then, in the second part, we show how we can derive Timed Computational Tree Logic formulae from Ob- ject Constraint Language-Real Time (OCL-RT) constraints. This formal veri�cation is performed by the Romeo model-checker. Finally, we illus- trate our approach through a case study derived from a RT asynchronous system (Integrated Modular Avionics/based airborne system).

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013

High-level architecture modeling languages, such as Architecture Analysis & Design Language (AADL), are gradually adopted in the design of embedded systems so that design choice verification, architecture exploration, and system property checking are carried out as early as possible. This paper presents our recent contributions to cope with clock-based timing analysis and validation of software architectures specified in AADL. In order to avoid semantics ambiguities of AADL, we mainly consider the AADL features related to real-time and logical time properties. We endue them with a semantics in the polychronous model of computation; this semantics is quickly reviewed. The semantics enables timing analysis, formal verification and simulation. In addition, thread-level scheduling, based on affine clock relations is also briefly presented here. A tutorial avionic case study, provided by C-S, has been adopted to illustrate our overall contribution.

13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Proceedings, 2007

Each domain has its own interpretation of time. We propose to extend UML, which is more and more used in the domain of real-time embedded applications, with a concept of time inherited from reactive system modeling : multiform time.

Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011), 2011

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a mathematically expressive model of time, the Clock Constraint Specification Language (CCSL), to specify timed annotations on UML diagrams and thus provides them with formally defined timed interpretations. Thanks to its expressive capability, the CCSL allows for the specification of static and dynamic properties, of deterministic and non-deterministic behaviors, or of systems with multiple clock domains. Code generation from such multiclocked specifications (for the purpose of synthesizing a simulator, for instance) is known to be a difficult issue. We address it by using the approach of controller synthesis. In our framework, a timed CCSL specification is regarded as a property whose satisfaction should be enforced for any UML diagram carrying it as annotation. To do so, CCSL statements are first translated into dynamical polynomial systems. Such systems can be manipulated using the model-checker Sigali to synthesize an executable property (a controller) which enforces the satisfaction of the specified timing constraints on the UML diagram with which it is executed.