Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

Journal of Signal Processing Systems, 2012

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time-through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources-and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

Lecture Notes in Computer Science, 2008

Given the scale and complexity of today's systems, it is of increasing importance that they handle and manage system's problems on their own in an intelligent and autonomous way. To cope with all nondeterministic changes and events that dynamically occur in a system's environment, a new "self-managing based" design approaches must be developed. Within this framework, an architectural network-based approach can be a good solution for the high demanding computation and self-managing needs. In this paper, we present the basic concept of such a design approach, its main properties and uses. A case study that proves the feasibility of this approach is demonstrated and validated on a small image-processing application.

2016

During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM pro-cessor alongside with a Virtex-5 FPGA daughter-board. While partial reconfigura-tion in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The pa-per discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogu...

IEEE Micro, 2014

International Journal of Computer Applications, 2014

A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance hardware. FPGAs are generally employed to construct a reconfigurable block as it provides an instant timeto-market advantage. Reconfigurable devices like FPGA offers improved computational efficiency as compared to traditional processor architectures. Reconfigurable block in these architectures provides the required flexibility for a large variety of embedded applications. Design space exploration of reconfigurable block involves a wide range of alternatives like logic block granularity in FPGA, interconnect topology, etc. The goal of this paper is to explore the reconfigurable architectures.

2013

— Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the flexibility and adaptability characteristic of software. While reconfigurable systems create new opportunities for engineering and delivering high-performance programmable systems, the traditional approaches to programming and managing computations used for hardware systems (e.g. Verilog, VHDL) and software systems (e.g. C, Fortran, Java) are inappropriate and inadequate for exploiting reconfigurable platforms. To address this need, we develop a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details (e.g., timing, device capacity, microarchitectural implementation details) and consequently allowing applications to scale to exploit newer, larg...

2005

We report on work-in-progress that aims to provide a run-time management kernel for applications running on FPGAs with embedded CPUs. We describe the global con-cept, the organization of the hardware environment for the reconfigurable modules and the reconfiguration strategy supported by the run-time management kernel. Practical issues concerning the implementation of the system on a Virtex-II Pro-based board are also addressed. 1.

International Journal of Electronics, 2007

Now a day's many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical Faults and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the brief discussion about the occurrence of different faults and various methods to remove those faults.

Computer, 2008