Network on a Chip

Many Processor Systems-on-Chip (MPSoC) have become tremendously complex systems. They are more sensitive to variability with technology scaling, which complicates the system design and impact the overall performance. Energy consumption is also of great interest for mobile platforms powered by battery and power management techniques, mainly based on Dynamic Voltage and Frequency Scaling (DVFS) algorithms, become mandatory. A Globally Asynchronous Locally Synchronous (GALS) design alleviate such problems by having multiple clocks, each one being distributed on a small area of the chip (called island), whereas an Asynchronous Network-on-Chip (ANoC) allow to communicate between the different islands. A robust technique is proposed to deal with a GALS-ANoC architecture under process variability constraints using advanced automatic control methods. The approach relaxes the fabrication constraints and help to the yield enhancement. Moreover, energy savings are even better for the same perceived performance with the obtained variability robustness. The case study is an island based on a MIPS R2000 processor implemented in STMicroelectronics 45nm technology and validated with finegrained simulations.

In this paper we present an energy-efficient solution for nanometric systems, where some variability problems which did not influence the circuit at a higher scale introduce some uncertainties at a sub-micrometric size. Therefore, some advanced control strategies are required to manage the energyperformance tradeoff in such an environment. The setup is based on some Dynamic Voltage and Frequency Scaling (DVFS) techniques applied to a Globally Asynchronous Locally Synchronous (GALS) architecture. Whereas a Vdd-hopping converter is able to provide discrete voltage levels, a Programmable Self-Timed Ring (PSTR) oscillator allows a variability robust source for generating adjustable clock frequencies. A fast predictive control law is also developed in this paper to calculate the frequency and voltage levels to apply to these actuators, minimizing the high voltage running time while ensuring good computational performance. Finally, the proposal is dedicated to a GALS node based on a MIPS processor over STMicroelectronics 45 nm technology and some fine-grained simulation results are performed. Besides a noticeable reduction of the energy consumption, the performance of the closed-loop system is ensured and a strong robustness to technological variability is also demonstrated.

Network-on-chip (NoC) paradigm, which is based on a modular packet-switched mechanism, effectively addresses many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth of many-core systems. In designing an efficient NoC, topology and routing algorithm are the most important challenging issues that have significant impact on area, latency and power consumption. The goal of this paper is designing a fuzzy-based routing algorithm for a NoC architecture with honeycomb topology. The proposed algorithm is a livelock and deadlock free routing algorithm based on fuzzy logic for hexagonal zones with flat triple coordinate system. The analysis of simulation results demonstrates that the proposed algorithm, provides higher performance in terms of latency, power consumption, throughput and area than a traditional fuzzy-based routing algorithm for mesh-based NoC architectures. Comparing to a non-fuzzy routing algorithm for honeycomb NoCs, the pro...

Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. Typically, these systems require fully balanced clock distribution trees to enable synchronous communication between all nodes on-chip, resulting in higher power consumption. One approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) mesochronous clocking scheme. NoCs implemented with a GALS clocking scheme, however, tend to have high latencies as packets must be synchronized at every hop between source and destination. In this paper, we propose a novel router microarchitecture for GALS NoCs which offers superior performance versus typical synchronizing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology that leverages the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 11%.

In this paper, we present a tool to analyse photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical simulator, based on the finite elements method, and a typical EDA layout editor has been realized.

Bufferless NoCs have emerged as a solution to reduce power and area by eliminating buffers used for routing. Such networks handle contention using packet dropping or deflection. In this paper, we study the effect of MaxFlex selection function on 2D bufferless meshes for both a fixed and a variable step size. For fixed step size, we perform an analytical study for the effect of using MaxFlex with different step size on the performance of 2D bufferless meshes. The analysis indicates that, as the step size increases the traffic in the central part of the network bisection relaxes. Simulation results show that, both average packet latency and average deflection count decrease as the step size used increases. Additionally, over different sizes of meshes, the results show that the network performs best if the step size is equal 60-80% of the mesh dimension. Then, we consider using variable step size in which a packet is routed using a step size dependent on the Manhattan distance, d, between the source and destination. Simulation results show that, using MaxFlex, a step size of 60% of the distance d enhances the packet latency over using fixed step size, straight line selection function and random productive port selection function by around 29%, 97% and 99% respectively.

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free ...

Many fault tolerance techniques have been proposed in Network on Chip to cope with defects during fabrication or faults during product lifetime. Fault tolerance routing algorithm provide reliable mechanisms for continue delivering their services in spite of defective nodes due to the presence of permanent and/or transient faults throughout their lifetime implementation. This paper presents a new approach in the domain of fault-tolerant NoC with two main contributions. Firstly, we consider a unified fault model that include transient faults, permanent faults and congestion considered as a fault. Secondly, we present a new architecture based on sub-nets and give an overview of the associated test and (re)routing algorithm. The main result of this paper, is a new routing algorithm called Collaborative Routing Algorithm for Fault Tolerance in Network on Chip (CRAFT-NoC). We compare our approach with ACO-FAR that considers as well congestion and permanent faults. Our simulation results show significant improvements in terms of both latency and reliability.

Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification of circuit-switched NoC's, which provide a dedicated channel for all communications with full bandwidth and thus are found to be more efficient than packet-switched NoCs in many contexts. In particular, the paper presents a generic methodology for the formal verification of circuit-switched NoC using the SPIN model checker. The proposed methodology provides generic modelling guidelines and identifies some properties, including deadlock freedom, starvation freedom, mutual exclusion and liveness, that are quite useful in the context of circuit-switched NoC. For illustration purposes, we use our methodology to verify the programmable NoC (PNoC) architecture, which is one of the most widely used circuit-switched NoC.

Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification of circuit-switched NoC's, which provide a dedicated channel for all communications with full bandwidth and thus are found to be more efficient than packet-switched NoCs in many contexts. In particular, the paper presents a generic methodology for the formal verification of circuit-switched NoC using the SPIN model checker. The proposed methodology provides generic modelling guidelines and identifies some properties, including deadlock freedom, starvation freedom, mutual exclusion and liveness, that are quite useful in the context of circuit-switched NoC. For illustration purposes, we use our methodology to verify the programmable NoC (PNoC) architecture, which is one of the most widely used circuit-switched NoC.

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-onchip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs 1.29× power and 2.19× area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.

IP-based platforms with Network on Chip (NoC) are one solution to support complex telecommunication applications. In this context, NoC architectures targeting high throughput applications tend to have configurable Network Interfaces (NI) and routers for reuse and performance purposes and aims at providing advanced communication and computation services. Unfortunately, these Network Interfaces are increasingly complex to parameterize and to program, while the deployment tools taking into account the low level architectural details are still non existent. This work focuses on providing methods and tools to easily and efficiently deploy applications on IP and NoC based platform with configurable NI. Configurable NI offer primitives to synchronize and schedule the communication and the behaviour of IPs. Our code generation flow takes as inputs an abstract model of the HW platform, of the application and of the mapping, and generates most of the required configurations. The efficiency of the approach is illustrated by the deployment of a complex 4G telecommunication application on a heterogeneous IP-based platform. I.

Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]- are published in general and textbooks are also available on the topic [8]- . There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut . papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. Mostly synthetic traffic patterns are used to imitate the functionalities of real cores. With the help of results of latency,

Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and the optimization of performance and cost metrics. These metrics mainly include power, reliability, area, thermal distribution and delay. A state-of-the-art mapping technique for NoC is introduced with the name of sailfish optimization algorithm (SFOA). The proposed algorithm minimizes the power dissipation of NoC via an empirical base applying a shared k-nearest neighbor clustering approach, and it gives quicker mapping over six considered standard benchmarks. The experimental results indicate that the proposed techniques outperform other existing nature-inspired metaheuristic approaches, especially in large application task graphs.

Network-on-Chip (NoC) has been unfolded as a superior alternative for integrating a considerably greater extent of cores on a single chip. Recently, multi-core systems have become prevalent because of the increased processing demands for high-performance embedded applications. Application mapping techniques play a significant role in enhancing the extensive performance of such complex multicore platforms. Developing and implementing efficient application mapping techniques are required for system design to meet the demand of such complicated multi-core systems. The paper primarily focuses on dynamic application mapping techniques, classifying them into a number of subcategories. It highlights such approaches and techniques that aim to enhance the performance of the NoC-based systems by optimizing them in terms of communication cost, latency, energy consumption, power, execution, and computational time. Future challenges, trends, and simulation tools have also been spotlighted. INDEX TERMS Network-on-chip, application mapping, system-on-chip, VOPD.

System-on-Chip design is facing increasing challenges in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. Chip designers are thus turning their attention to Network-on-Chip solutions. Packetswitches play a key role in interconnection networks and this paper focuses on their implementation as asynchronous circuits. The results of experiments run to evaluate several aspects of the routing switch implementation are presented.

This paper presents the concept and design of exhaustive-parallel search algorithm for Network on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 8X8 mesh architecture and its performance is evaluated.

As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to manycores, the role of the interconnection communications becomes more critical. The number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the International Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented with m×n 2-D mesh topology connecting small size routers. This will represent the bottleneck to the communication latency for the increasing number of cores where the average number of hops the data have to pass will increase. In this paper, we propose an alternative NoC interconnecting scheme by using large routers interconnecting large number of cores in star topology. This interconnection scheme can be scaled up by using hierarchical-star or fat-tree topologies. We present the implementation and performance evaluation of three large router architectures and compare their efficiency to the small 5×5 router used in the mesh topology. We develop a simulating environment that resembles the real NoC conditions to test the routers throughput and average latency on different buffer sizes and under different traffic loads. We also synthesize them to estimate the area and power consumption. Then, routers efficiencies are calculated with respect to the area and power consumption.

This paper proposes an offline test strategy for finding the largest fault-free connected sub-structure of a mesh-based NoC. Faulty switch ports are found by flooding the NoC with test packets. Then, NoC routers are reconfigured according to the degraded NoC structure to route incoming packets.

Este trabalho apresenta e descreve um protocolo adaptativo de coerência de cache baseado nos esquemas "snoopy" para um sistema multiprocessador de memória compartilhada baseado na hierarquia de barramentos. O protocolo permite diminuir o tráfego adicional na rede produzido pelas ações de coerência e se adapta dinamicamente ao compartilhamento e aos padrões de referência que variam amplamente para os diferentes programas aplicativos. A sua avaliação de desempenho é feita com uma análise comparativa com os protocolos Dash e SCI (baseados em esquemas diretórios).

A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as well as routing methodologies capable to handle routing in a NoC with obstacles created by dynamically placed components. We prove the unrestricted reachability of components and pins, the deadlock-freeness and we finally show the feasibility of our approach by means on real life example applications.

In this article, we present CuNoC, a new paradigm for intercommunication between modules dynamically placed on a chip for FPGA-based reconfigurable devices. The CuNoC is based on scalable communication unit called CU which allows the simultaneous communication between several processing elements placed on the chip. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main NoC approaches already proposed.

A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication infrastructure, components placed at run-time on a device can mutually communicate. A 4x4 dynamic network-on-chip communication infrastructure prototype, implemented in an FPGA occupies only 7% of the device area and can be clocked at 391 MHz.

A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at runtime is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as well as routing methodologies capable to handle routing in a NoC with obstacles created by dynamically placed components. We prove the unrestricted reachability of components and pins, the deadlock-freeness and we finally show the feasibility of our approach by means on real life example applications.

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.

This paper presents an on-chip network for a run-time reconfigurable System-on-Chip. The network uses packetswitching with virtual channels. It can provide guaranteed services as well as best effort services. The guaranteed services are based on virtual channel allocation, in contrast to other on-chip networks where guarantees are provided by time-division multiplexing. The network is particularly suitable for systems in which the traffic is dominated by streams. We model the data traffic in the system and simulate the behaviour of the network with this model. The results show that the network is capable of handling the system traffic and can provide the required guarantees. Advances in silicon technology bring, among others, two problems that chip designers have to face -a high design complexity and a signal integrity problem [1],[2], . The first problem is the concern that the complexity of a system that fits on a single chip is getting so high that the time needed to design a completely new system using the current design methods and tools is becoming impractical long. For that reason it is foreseen that future System-on-Chip (SoC) will be based mostly on pre-designed IP blocks relying on extensive IP reuse. To be practical, such a design methodology needs to be complemented with a unified and simple solution for interconnecting and integrating IP blocks in a system. Currently on-chip buses offer such a solution, but since the bus bandwidth does not scale with the number of IP cores on the chip it will soon become a system bottleneck. The second problem, the signal integrity problem, is due to the fact that with the technology scaling transistors get smaller and faster while wires get thinner and slower. Wire delay becomes proportional to the wire length and a few long wires on a chip can degrade the performance of the entire chip. Thus, the on-chip interconnects become a limiting factor for SoC performance and their physical parameters * This research is supported by the research program of the Dutch organisation for Scientific Research NWO (project number 612.064.103) and the EU-FP6 project 4S (IST 001908

The Open Core Protocol (OCP) delivers the only non-proprietary, openly licensed, core-centric protocol that comprehensively describes the system level integration requirements of intellectual property (IP) cores. While other bus and component interfaces address only the data flow aspects of core communications, the OCP unifies all inter-core communications, including sideband control and test harness signals. The OCP's synchronous unidirectional signaling produces simplified core implementation; integration and timing analysis.OCP eliminates the task of repeatedly defining, verifying, documenting and supporting proprietary interface protocols. The OCP readily adapts to support new core capabilities while limiting test suite modifications for core upgrades. Clearly delineated design boundaries enable cores to be designed independently of other system cores yielding definitive, reusable IP cores with reusable verification and test suites.

NoC(network On Chip) is an efficient approach to design the communication subsystem between IP Cores in SoC(System On Chip). In this paper a communication infrastructure design using CDMA (Code division multiple access) based shared bus architecture for core-to-core communication in NoC is presented. CDMA has been proposed as an alternative way for interconnect of IP cores in a SoC design, or as a solution for interconnecting modules within a system realized in several PCBs. Compared to conventional TDMA-based bus this paper present how a multiprocessor system can benefit from the use of concurrent data transfers.The simulation of the system using VHDL code is carried out. The performance of the system is evaluated.

Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits. However, insufficient effort has been made for hardware Trojans (HTs) in the network-on-chip. In this study, we implement a countermeasure to congeal the networkon-chip hardware design in order to prevent changes from being made to the network-on-chip design. We propose a collaborative method which uses flit integrity and dynamic flit permutation to eliminate the hardware Trojan inserted into the router of the NoC by a disloyal employee or a third-party vendor corporation. The proposed method increases the number of received packets by up to 10% more compared to existing techniques, which contain HTs in the destination address of the flit. Compared to the runtime HT mitigation method, the proposed scheme also decreases the average latency for the hardware Trojan inserted in the flit's header, tail, and destination field up to 14.7%, 8%, and 3%, respectively.

This paper reports the results of applying metrics to hypermedia authoring under the SHAPE research project. The aim of SHAPE is to help authors develop high quality large hypermedia applications for education. The quality characteristics considered are the reusability of information, the maintainability of applications and the authoring effort. Although a number of metrics for hypertext systems have been proposed, we believe that many of the measures proposed in the past lack the necessary mathematical and/or ...

This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.

An important aspect of communication network development has been the reduction in cost and the improvement in speed and quality of transmission link .A topological network design problem is solved by selecting the subset of links while minimizing the total cost subject to k connectivity and diameter constraint. Diameter is set to two links only as we want to design a fast network whose speed would be comparable to the complete connected network (having the diameter of one link) at low cost. A fault tolerant network is able to maintain connectivity under the failure condition only if there are multiple links disjoint paths for each node pair. Designing is a well-known optimization problem and difficult to solve. For N number of nodes, maximum numbers of links are n*(n-1)/2, and the maximum number of topological configurations of n nodes are 2 n*(n-1). I.

It is widely known that the SDR industry campaigns component-based radio applications, which will enable fast prototyping and deployment of new radio devices and may increase manufacturing profits. Through the JTRS program, the US Dept. of Defence proposed the SCA specification as the standard for military communications. The SDR Forum is now reviewing these specifications and trying to adapt them to the commercial market. The significant differences between military and commercial communications' requirements make this migration a hazardous task. On the other hand, the SCA specification does not consider any method or procedure that enables cognitive functionalities, which would be necessary for future cognitive radio implementations. This paper therefore presents an alternative approach to SCA, introducing a lowprofile operating environment for next generation cognitive radios. We demonstrate its suitability for present and future commercial radios.

Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. This paper proposes to deploy sleep transistor insertion (STI) in the clock tree of datapaths in ASICs or in general-purpose processors in order to reduce leakage power. It characterizes the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. It then uses these characteristics during leakage power optimization. It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. The potential benefits of STI in ASIC design are evaluated using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after the clock synthesis and place-and-route of the benchmark circuits. The results show that the clock tree leakage power is reduced by 19-32% depending on the topology of the synthesized clock tree. We also apply PSSTI in the clock tree of the datapaths in general-purpose processors using architectural control of the sleep mode. This achieves a reduction in the leakage power and the dynamic power of the clock tree within different datapath components (adder, multiplier, etc.) of as much as 80%. This approach is also applicable to other on-chip structure where inverters are large in size and commonly used, e.g. SRAMs or networks-on-a-chip, which combined with the clock tree savings will significantly reduce processor or ASIC overall power consumption.

With the possibility of integrating multiple cores into a single chip, research on the networks-on-chip (NoCs) as a kind of interconnection network has assumed great significance. In such networks, the effort is to provide broadband and extendable infrastructure for multi-core architectures. Communication between processors in an NoC is established using routing algorithms. Meanwhile, NoCs, like any other system, are prone to failure. With the increase in the number of network components on a chip, the probability of failure increases, too. Therefore, considering a fault-tolerant mechanism in NoCs seems to be a necessity. The main challenge of this work is combining performance and fault tolerance while reducing power, complexity and cost. In this paper, a fault-tolerant routing algorithm for tolerating static and dynamic faults in 2D Mesh NoCs and node failure model is presented. It should be taken into consideration that despite many other routing algorithms, the proposed method uses only one Virtual Channel. Results show that this method has lower latency and power consumption than SAVA and segment-based (SB) routing algorithms. It showed 2.91 and 12.74 % less power consumption than SAVA and SB, respectively, under SPLASH-2 traffic in an 8 $$\times $$× 8 Mesh network with 8 faulty nodes. Its average latency, under Uniform, Transpose, and SPLASH-2 traffics in a 4 $$\times $$× 4 Mesh with 4 faulty nodes and an 8 $$\times $$× 8 Mesh network with 8 faulty nodes, was reduced by 4.39 and 14.08 % compared to SAVA and SB, respectively.

The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC[4] coder and multi-FPGA platforms [12][13]. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.

A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the propo...

Electrical network-on-chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Re-cent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and an electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC). In this paper, we propose a predictive switching and a reservation based path setup techniques to reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By using these techniques, it is possible to reduce the latency for end-to-end communication in a HPNoC improving its overall performance. In the simulation, we use a cycle accurate simulator under uniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The results show that the proposed techniques considerably improve the overall latency of HPNoC.

This research explored the impact of religious, cultural, and traditional beliefs on Arab Muslims' understanding of mental disorders and their treatment, with a particular emphasis on the role of Islamic theology. Employing an exploratory sequential mixed-methods design, the study first conducted qualitative semi-structured interviews with 12 Arab Muslim participants (6 men and 6 women) to examine their mental health perspectives. Thematic

The number of cores in a single chip increases with the increase of communication needs. Network on Chips (NoCs) are developed to handle these needs. We present our work to evaluate models of NoC present in the SoCLib library with the NoCBench platform. NoCBench contains performance evaluation tools for NoC such as a Transaction Generator and an Execution Monitor. SoClib is a library of IP cores, including NoC, written in SystemC, we retain the WiNoCoD RF-NoC as a use case. Various benchmarks can be ported to our NoC to evaluate its performance and it can be compared with existing NoCs which used the same performance evaluation tools under NoCBench.

In this paper we present a method for mapping streaming applications, with real-time requirements, onto a reconfigurable MPSoC. In this method, the performance of the hardware architecture (the reconfigurable Processing Element, the Network Interface and the Network-on-Chip) is integrated in the performance models of the applications. In this way the performance of the mapped application can be determined at runtime. A predictable NoC (guaranteed bandwidth and bounded latency), a predictable Network Interface and a predictable Processing Element are key requirements for our approach.

Multi-Processor System on Chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on Chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instantiate such a NoC-based MPSoC platform in a systematic and automated way. In this paper we present an integrated flow to automatically generate a highly configurable NoC-based MPSoC for FPGA instantiation. The system specification is done on a high level of abstraction, relieving the designer of errorprone and time consuming work. The flow uses the state-ofthe-art AEthereal NoC, and Silicon Hive processing cores, both configurable at design-and run-time. We use this flow to generate a range of sample designs whose functionality has been verified on a Celoxica RC300E development board. The board, equipped with a Xilinx Virtex II 6000, also offers a huge number of peripherals, and we show how their insertion is automated in the design for easy debugging and prototyping.

As changes are made to an object-oriented design, its structure and/or behavior may be affected. Modifications made to one class can have ripple effects on other classes in the design. The stability of an objectoriented design indicates its resistance to interclass propagation of changes that the design would have when it is modified. There are two aspects of design stability: logical stability and performance stability. Logical stability is concerned with design structure, whereas performance stability is concerned with design behavior. In this study, the object-oriented design metrics proposed by Chidamber and Kemerer were adopted as candidate indicators of the logical stability of object-oriented designs. The objective was to investigate whether or not there are correlations between these metrics and the logical stability of classes. The experimental results indicated that WMC, DIT, CBO, RFC, and LCOM metrics are negatively correlated with the logical stability of classes. However, no correlation was found between NOC metric and the logical stability of classes.

, which will consume extra energy. This paper is focusing on the energy-efficient design of input buffers, one of the most critical components in NoC. The energy efficient input buffer is proposed for NoC routers which reduce energy consumption more significantly as compared to conventional input buffer and also give reduction in delay. We use a 65nm CMOS process in our simulation.

, which will consume extra energy. This paper is focusing on the energy-efficient design of input buffers, one of the most critical components in NoC. The energy efficient input buffer is proposed for NoC routers which reduce energy consumption more significantly as compared to conventional input buffer and also give reduction in delay. We use a 65nm CMOS process in our simulation.