Asynchronous Packet-Switching for Networks-on-Chip

16th International Conference on VLSI Design, 2003. Proceedings., 2003

With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key contributors to latency. With the goal of reducing this latency we examine the packetization strategies in the NoC communication. In this paper, three schemes of implementations are analyzed, and the costs in terms of latency, and area are projected through actual synthesis. 2. Background Work The concept of SoC (System-on-Chip) network communication in the form of packet switched communication was first discussed by Guerrier and Greiner[3]. Their paper presented an architectural study of a scalable system-level interconnect template. They proposed a generic interconnection template that

Advances in Radio Science, 2008

Future Systems-on-Chip (SoC) will consist of many embedded functional units like e.g. embedded processor cores, memories or FPGA like structures. These SoCs will have huge communication demands, which can not be fulfilled by bus-based communication systems. Possible solutions to this problem are so called Networks-on-Chip (NoC).

INTEGRATION, the VLSI …, 2004

His main research topics are digital systems design and fast prototyping, digital systems physical synthesis CAD, telecommunication applications, hardwaresoftware codesign. He is a member of the Hardware Design Support Group (GAPH) at the PUCRS. N. L. V. Calazans works at the PUCRS/Brazil since 1986. He is a professor since 1999. His main research topics are digital systems design and fast prototyping, hardware-software codesign, telecommunication applications. He is the head of the Hardware Design Support Group (GAPH) at the PUCRS.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009

Microprocess. Microsystems, 2018

Networks-on-Chip (NoCs) are now being used to provide inter-core communication for manycore Systems-on-Chip (SoCs). This is because traditional on-chip interconnects do not scale with increasing number of cores. Typical NoCs dedicate a set of buffers to their input and/or output ports. This can lead to buffer under-utilization for applications with non-uniform traffic characteristics. In order to provide improved buffer utilization for performance gains and energy efficiency, we have proposed the Roundabout-NoC (R-NoC) concept. R-NoC is inspired by real-life multi-lane traffic roundabouts. It consists of lanes shared by multiple input/output ports. This allows the buffers to be exploited for performance gains by data-flows from multiple input ports. This work extends the asynchronous evaluation of the R-NoC , named R-NoC-A . The router is evaluated using 45 nm CMOS technology. The R-NoC-A router achieves a throughput of 465 Mflit/s and a network saturation throughput of 129 Gbps on ...

Journal of Applied Research and Technology, 2014

The use of on chip networks as interconnection media for systems implemented in FPGAs is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the performance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aimed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4-device. We also provide a performance profile, obtained by subjecting a network formed by these switches to different synthetic workloads within a simulator. This simulator was developed as part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional bus-based architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

2009 International Conference on Advanced Technologies for Communications, 2009

The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.

Abstract The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to concatenate IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a packet-switched router targeted to a mesh interconnection topology.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008

The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard application-specific IC flow. This design is considered across a range of IC interconnect scenarios. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect by removing the need for clocked inter-block pipeline stages, while maintaining high throughput. Further results demonstrate a computer-aided design tool enhancement that would significantly increase this space. A detailed comparison of power, area, and latency of the two strategies is also provided for a range of IC scenarios. Index Terms-Asynchronous logic circuits, design automation, interconnection networks, network-on-chip (NoC), system-on-chip (SoC). I. INTRODUCTION T HE IMPLEMENTATION of interconnect is becoming a significant issue in modern integrated circuit (IC) design. In older processes, wire delays were not significant when compared to gate delays. This greatly simplified inter-block communication since any part of the IC could communicate with any other part without special timing considerations. However, in modern processes, wire delays are significant, and inter-block communication is no longer a simple matter [1]. Without careful design, interconnect may become the critical path on a given IC and limit overall performance. Repeater insertion has been employed to decrease wire latency and improve performance [2]. However, even optimally placed buffers may not be sufficient, and register pipelining is required in some situations [3]. Although register pipelining increases throughput, there is a significant design effort required to implement these synchronous pipeline stages since each individual register requires a lowskew clock. Asynchronous techniques have been suggested as a potential solution to the problem of IC interconnect [4], [5]. These asynchronous techniques do not require a global clock.