Packet Routing in Dynamically Changing Networks on Chip

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm which can enhance the NoC communication performance with minimal energy overhead. In particular, our proposed NoC architecture exploits the following two features: i) self-reconfigurable bidirectional channels to increase the effective bandwidth and ii) express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. A deadlock-free and traffic-aware dynamic routing algorithm is further developed for the proposed architecture, which can take advantage of the increased flexibility in the proposed architecture. Both the channels self-reconfiguration and routing decisions are made in a distributed fashion, based on a function of the localized traffic conditions, in order to maximize the performance and minimize the energy costs at the macroscopic level. Our simulation results show that the proposed approach can reduce the network latency by 30% -80% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15% power overhead.

2011

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters unpredictable, heterogeneous and time dependent traffic loads. This motivates the introduction of adaptive routing mechanisms that balance the NoC's loads and achieve higher throughput compared with traditional oblivious routing schemes. An effective adaptive routing scheme should be based on a global view of the network state. However, most current adaptive routing schemes, following off-chip networks, are based on distributed reactions to local congestion. In this paper we leverage the unique on-chip capabilities and introduce a novel paradigm of NoC centralized adaptive routing. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. We present a specific design for the case of mesh topology, where XY or YX routes are adaptively selected for each source-destination pair. We show that while our implementation is lightweight and scalable in hardware costs, it outperforms oblivious and distributed adaptive routing schemes in terms of load balancing and average packet delay. †

International Journal of Power Electronics and Drive Systems, 2024

The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable twodimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.

2005

With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnect infrastructure, the "Network on chip (NoC)" concept was introduced. With network methodologies coming on-chip, various characteristics of traditional networks come into play. So far, failures that are common in regular networks were hardly considered onchip; this paper introduces ideas of dynamic routing in the context of NoCs and explains how they could be applied to cope with adverse physical effects of deep sub-micron technology.