Implementation of Energy-Efficient Input Buffer for NoC Router

International Journal of Advanced Trends in Computer Science and Engineering, 2020

To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia data at low latency and high throughput. These NoC's was designed and developed the chips for both 2D and 3D which includes switching, routing and crossbar techniques, out of which routing algorithms are plays major role due to the computational operations take place here and produce the different delay. In turn these delays are affected on throughput and latency. Many of the NoC's has buffered and bufferless routers to optimize the area, power consumption and latency. Therefore the detailed literature survey has been done mainly on latest buffered and bufferless NoC's with different routing algorithms used for addressing the major constraints like QoS, throughput, latency and hardware utilizations for different injection rates. As per requirements at present situation for better communication within core networks, this paper mainly focused on commonly used architectures and their inter components connectivity's that can deal with methodologies and design challenges for optimization of signal integrity, scalability, throughput and latency in an NoC's. At the last, modified buffered and bufferless NoC architectures are proposed which includes the modified routing algorithm called Dynamically buffered and bufferless reconfigurable NoC (DB 2 R-NoC's) and feasible direction finding (FDF) for switching. Making use of these architectures, any dimensions of NoC's can be designed and can validate for multimedia data and also can test on Field Programmable Gate Array (FPAG) processors.

International Journal of Engineering and Technology, 2016

The traditional system on chip designs employ the shared bus architecture for data transfer in highly integrated Multiprocessor system on chips(MPSoC).Network on chip (NoC)is a new paradigm for on chip communication for Multiprocessor systems on chips(MPSoCs). NoCs replace the traditional shared buses system with routing switches. Heart of the NoC is the router and it consists of an input buffer, arbiter, crossbar and an output port. The NoC router uses a buffer to store the incoming packets. These buffers improve the performance but they consume more power and area. Bufferless deflection routing is the solution for improvement in energy efficiency. In this method deflections of the packets take place to overcome the contention problem. But at high network load, deflection routing degrades the performance because of unnecessary hopping of data packets. The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing. In this paper the input block of MinBD router is implemented on FPGA which shows that a small buffer will help to reduce the network deflection rate. It also improves the performance and energy efficiency while buffering only deflected data packets. Keywords-MPSoC, NoC, Router, Minimally buffered deflection router (MinBD),FPGA I. INTRODUCTION As technology scaling allows the integration of billions of transistors on a chip, it evolves MPSoC architectures which allow more processors and more cores to be placed on a single chip. Usually for MPSoC architectures, interconnections among various devices or cores are based on shared bus. Share bus architecture allows only one communication transaction at a time. Hence scalability is a major concern with shared bus system. A solution for such communication bottleneck is use of switching network, NoC(Network on chip) to interconnect various cores of MPSoC [2]. NoC has emerged as scalable and suitable design approach to solve the interconnection problem for MPSoC architecture. NoC architecture consists of three main parts, namely routers, link and network interface through which cores are interconnected to the NoC. Router is the heart of NoC as it coordinates data packet propagation from source to destination port based on information received from scheduler. Router consists of input port, arbiter, crossbar and output port. In most of the router design, input port is having buffer to temporarily store data packets and then transfer to destination port through crossbar. These buffers improve performance in term of increasing the bandwidth efficiency but consume significant power. These buffers consume dynamic power when read/ write operation is taking place and static energy when they are empty. Secondly buffers occupy more chip network area. In the TRIPS prototype chip, input buffers of routers were occupying 75% of total on chip network area. Hence there is a need for bufferless routers which eliminate input and output buffers [3]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7]. Yu Cai et al. Prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or tours topology compared with buffered architecture [9]. CHIPPER NoC implementation shows that when compare with buffered routing, it reduces average network power by 54% and area by 36.2% for 8X8 mesh topology [5]. The key idea for bufferless routing is that data packets are never buffered in the network. When two packets contend for the same link, one is deflected. Thus Bufferless deflection routing causes unnecessary hopping of data packets for high network utilization. It increases data packets traversals and reduces network throughput and also increases dynamic power. MinBD (minimally buffered deflection routing) provides the solution for bufferless deflection routing [4]. This paper is organized as follows. In section II, we discussed working principle of MinBD deflection router. Implementation of efficient input block of router is presented in section III. In section IV, we evaluate our proposed design for various test cases. Router input block is implemented on FPGA. The conclusions are given in section V.

International Journal of Engineering Sciences & Research Technology, 2014

In this work focus on ‘Network on chip’ and “Multiprocessor system on chip” applications its a guaranteed supporting for network process to reducing the circuit area, lower power consumption, low cost, and increases the performance. Network employs multi-stage network approaches on packet switching and pipelined circuit switching. Based on packet switching need more buffers, area should be high. To overcome the occupy more area by using pipelined circuit switching reducing some buffers in a multiple networks, The proposed network employs CHIPPER (Cheap-Interconnect Partially Permuting Router) technique for using “bufferless deflection router” method. This bufferless deflection routers to eliminate route buffers and cross buffers. So Removing buffers yields more energy in network on chip.

2016

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the architecture itself and the communication links. In this paper, a survey is conducted on recent contributions and techniques employed by researchers towards the reduction of power in the router architecture, network architecture and communication links.

Wireless Communications and Mobile Computing

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

2010

In Networks-on-chip, increasing the depth of routers' buffers even by a few stages can have a significant effect on average latency and saturation threshold of the network. However, the price to pay could be high in terms of power and silicon area. In this paper, we propose a low power, high throughput asynchronous FIFO suitable for buffers of GALS NoC routers. We consistently compare the performance with regards to power, area and throughput of our FIFO with some different FIFO structures, by exploring their design trade-offs with various number of stages and for different data lengths. These structures are simulated in 90nm CMOS technology with accurate spice simulations, where results show a low power consumption and latency, with a higher throughput. Finally, a back-annotated HDL model of a 4x4 mesh network, wherein a fully asynchronous router is implemented, shows better average latency, saturation threshold and power tradeoffs, using the proposed FIFO.

International Journal of Engineering Research and, 2020

The on-chip network has become a significant solution for the communication limitation of SoC (System-on-chip). The demand for relative increment in bandwidth to facilitate high core utilization and the need for low power consumption as well as higher performance has increased. The major circuitry is the router in NoC, which barely affects on power dissipation, latency, and performance. The dynamic power consumption is one of the major components of total power consumption. This paper presents a detailed structure and verification of the router module and various power optimization techniques for NOC by restructuring the architecture. The design of the router is coded in Verilog, synthesized, and simulated in the Xilinx ISE Design Suite 19.1 tool.

Bulletin of Electrical Engineering and Informatics, 2019

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC's performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

IOSR Journal of Electrical and Electronics Engineering

In this paper, objective is to first characterize the need of a heterogeneous reconfigurable router and show how an NoC built with reconfigurable routers allows the use of buffers with smaller depths. These in turn have a similar performance w.r.t. an NoC using a fixed size router, the latter showing a large buffer depth and incurring lower efficiency than the design presented here which can also lead to higher power consumption than the project design. Considering the NoC components, as crossbars, arbiters, buffers, and links, in the experiments realized by [4] the buffers were the largest leakage power consumers, dissipating approximately 64% of the whole power budget. In this way, the buffers can be considered as candidates for leakage power optimization by handling the buffers efficiently and effectively, since even at high loads, there can be 85% of idle buffers [4]. Regarding dynamic power, the buffers' consumption is also high, and it increases rapidly as the packet flow throughput increases [5]. Therefore, this paper particular goal is to provide an NoC router with a certain amount of heterogeneous reconfiguration logic, allowing changes in the amount of buffer utilization in each input channel, in conformity with the communication needs. The principle is that each input channel can lend/borrow buffer units to/from neighbouring channels in order to obtain a determined bandwidth. When a channel does not need its entire available buffer, it can lend buffer word slots to neighbouring channels. The inefficiency in the amount of buffers used within a homogeneous router, and the gains that can be achieved using the proposed strategy can be shown at further level. The focus is on providing a reconfigurable router that can be tested to optimize power and improve energy usage while sustaining high performance, even when the application changes the communication pattern.

International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE), 2018

The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router architecture for NOC is designed for processing elements communicate over a second communication level using direct-links between another node elements. Several possibilities to use the router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.