Asynchronous Bypass Channel Routers

LASCAS 2015

Networks on chip (NoCs) are efficient infrastructures to enable communication among the large number of IPs that compose modern systems on chip (SoCs). However, even if recent technologies allow the construction of such complex systems, they increase the cost and effort of designing a correct and efficient chip-wide clock delivery network for a fully synchronous system. Asynchronous NoCs are an attractive alternative, as they allow each IP to operate on an independent clock domain, eliminating the need for a global clock network and producing globally asynchronous locally synchronous (GALS) systems. This paper details the design of a low power NoC router that is asynchronous and employs a transition-signaling bundled-data design style. Results show reductions of 27% in energy consumption when compared to a similar synchronous router.

Microprocess. Microsystems, 2018

Networks-on-Chip (NoCs) are now being used to provide inter-core communication for manycore Systems-on-Chip (SoCs). This is because traditional on-chip interconnects do not scale with increasing number of cores. Typical NoCs dedicate a set of buffers to their input and/or output ports. This can lead to buffer under-utilization for applications with non-uniform traffic characteristics. In order to provide improved buffer utilization for performance gains and energy efficiency, we have proposed the Roundabout-NoC (R-NoC) concept. R-NoC is inspired by real-life multi-lane traffic roundabouts. It consists of lanes shared by multiple input/output ports. This allows the buffers to be exploited for performance gains by data-flows from multiple input ports. This work extends the asynchronous evaluation of the R-NoC , named R-NoC-A . The router is evaluated using 45 nm CMOS technology. The R-NoC-A router achieves a throughput of 465 Mflit/s and a network saturation throughput of 129 Gbps on ...

Symposium on VLSI, …, 2008

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simulation at the RTL level with timing show that, even when submitted to large rates of traffic injection, the proposed NoC displays a significant reduction in switching activity and consequently in power dissipation.

International Journal of Radiation Oncology Biology Physics, 2004

This paper presents an asynchronous and a synchronous NoC router architecture. The asynchronous scheme is implemented by the help of CSP-Verilog language and the synchronous one is designed employing VHDL language. Their designs are similar except the extra links which are in charge of handshaking processes in asynchronous architecture. According to the experimental results the transition counts of buffer, and switch components in synchronous router are almost 82% and 60% of asynchronous one, respectively. On the other hand, the transition counting of routing unit in asynchronous NoC router is nearly 73% of synchronous one. Power consumption of them are evaluated according to the obtained transition counting. Based on the comparison the power consumption of buffer and switch components are almost same due to their similar structure. However, the power consumption of routing unit component in asynchronous design is lower than synchronous one.

IEEE Consumer Electronics Magazine, 2019

he ever-increasing demand for in-home products, automation, and sharing information over social networks has opened a gateway for consumer electronics (CE) devices. As a result, system on chip (SoC)-based multiprocessor systems are designed to meet the current demand. This article presents the architectural issues of multiprocessor SoCs (MPSoCs) used in CE devices and provides network on chip (NoC)-based multiprocessors as a solution that helps alleviate the performance of CE devices. Asynchronous NoC propounds more throughput and lower latency than synchronous NoC for a specific number of virtual channels (VCs) and cores. Network on Chip for Consumer Electronics Devices An architectural and performance exploration of synchronous and asynchronous network-on-chip-based systems.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2011

Router microarchitecture plays a central role in the performance of networks-on-chip (NoCs). Buffers are needed in routers to house incoming flits that cannot be immediately forwarded due to contention. This buffering can be done at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an output-buffered router (OBR). OBRs are attractive because they can sustain higher throughputs and have lower queuing delays under high loads than IBRs. However, a direct implementation of an OBR requires a router speedup equal to the number of ports, making such a design prohibitive under aggressive clocking needs and limited power budgets of most NoC applications. In this paper, a new router design based on a distributed shared-buffer (DSB) architecture is proposed that aims to practically emulate an OBR. The proposed architecture introduces innovations to address the unique constraints of NoCs, including efficient pipelining and novel flow control. Practical DSB configurations are also presented with reduced power overheads while exhibiting negligible performance degradation. Compared to a state-of-the-art pipelined IBR, the proposed DSB router achieves up to 19% higher throughput on synthetic traffic and reduces packet latency on average by 61% when running SPLASH-2 benchmarks with high contention. On average, the saturation throughput of DSB routers is within 7% of the theoretically ideal saturation throughput under the synthetic workloads evaluated.

International Journal of Reconfigurable Computing, 2015

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed No...

Abstract The downscaling of silicon technology and the capacity to build entire systems on a chip have made intrachip communication a relevant research topic. Besides, technology challenges point to the fast adoption of non-synchronous networks on chip (NoCs), using either globally asynchronous, locally synchronous (GALS) or even clockless approaches. However, clockless circuit design with current automation tools is challenging, due to the fact that most of these tools target synchronous (clocked) design styles.

2013 International Symposium on Rapid System Prototyping (RSP), 2013

The downscaling of silicon technology and the possibility of building MPSoCs, make intrachip communication a mainstream research topic. NoCs are an elegant solution to provide communication scalability and modularity. NoCs are already common in MPSoC design. Moreover, new technology challenges point to a growth in the use of non-synchronous NoCs. However, the design of asynchronous infrastructures with current EDA tools is challenging. That is due to the fact that most of these tools are oriented towards synchronous design. This work proposes and evaluates a fully asynchronous NoC router based on the Balsa language and framework. The design is validates through FPGA synthesis.

IEEE International SOC Conference, 2004. Proceedings., 2000

This paper presents an asynchronous on-chip network router with Quality-of-Service (QoS) support. The router uses a virtual channel architecture with a priority-based scheduler to differentiate between multiple connections with various QoS requirements sharing the same physical channel. A gate-level prototype of the router has been built and its functionality and performance evaluated. The simulations show that the router is capable of offering a high-level of QoS within the capacity limitations of the network.