MOSFET parameters Research Papers

Impact of MOSFET parameters on its parasitic capacitances

2025, Proceedings of the 6th WSEAS …

Impact of MOSFET parameters on its parasitic capacitances NEBI CAKA, MILAIM ZABELI, MYZAFERE LIMANI, QAMIL KABASHI Faculty of Electrical and Computer Engineering University of Prishtina 10110 Prishtina, Fakulteti Teknik, Kodra e Diellit,... more

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Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry

by Sarita Misra

2024, Journal of Computational Electronics

As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless... more

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WITHDRAWN: Visualization of gate-bias dependent carrier distribution in SiC power-MOSFET using super-higher-order scanning nonlinear dielectric microscopy

by Yasuo Cho

2024, Microelectronics Reliability

Carrier distributions in cross-section of operated SiC power MOSFET were measured using super-higher-order scanning nonlinear dielectric microscopy. Two measurements were carried out; depletion layer distribution analysis for "on"/"off"... more

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Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

by Anup Sarkar

2023, Microelectronics Journal

A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects... more

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Parameter extraction and modelling of short-channel LDD MOSFETs for VLSI applications

by M. Deen

2023, Proceedings of Canadian Conference on Electrical and Computer Engineering

We report on the effects of temperature and biasing voltages on the parasitic resistance (Rp) and channel length reduction (AL) parameters in short-channel lightlydoped drain (LDD) NMOS transistors. These two parameters and their... more

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Nebi Caka

2023

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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Role of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static and switching conditions of operation

by Nebi Caka

2023

The aim of this paper is to show the influence of the threshold voltage and transconductance parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static and switching conditions of operation, as well as... more

Fig. 1 NMOS inverter configuration with depletion type NMOS- load. 1 Introduction Key words: NMOS inverter, NMOS transistor, VTC characteristics, threshold voltage, critical voltages, nois« margins, NMOS transconductance parameter, propagation delay times.

Using drain currents of NMOS transistors in NMOS inverter depending on the input voltage levels, respectively output voltage levels, and the necessary conditions to determine the critical values can be derived expressions for the critical voltage values at the input and output of NMOS inverter, as: The values of output critical voltage Vo, are found using the numerical interaction between expressions (1) and (3), while the input critical voltage values Vi, and V;;; are found using the numerical interaction between expressions of the output voltage and the expressions for the critical values of voltage at the input. Interaction methods enable convergence of voltage critical values to the correct values. Also, static power dissipation which appears to output in low state (Vo,) depends on parameters of NMOS transistor as load [12].

Fig. 2 The NMOS-inverter with equivalent lumped capacitive load. The performance of NMOS inverter during switching conditions evaluate by propagation delays of output voltage related by input voltage. Propagation delay times are dependent on the physical and electrical parameters of the NMOS transis calculate propagation delay times will be used the NMOS inverter with an equivalent lumped linear capaci ground equivalent lumped capacitance will be called the load capacitance, which is the sum of parasitic ors which construct the NMOS inverter. To ance, connected between the output node and (C,; capacitance) shown in Fig. 2. The capaci ance components that appear in NMOS inverter.

The propagation delay time of the output voltage during the transition from high-to-low level tpy,, when the input voltage switches from low-to-high level (with negligible rise time), calculate based in Propagation delay times during transition output voltage from low-to-high level tp_y, when input voltage have transition from high-to-low level (when the fall time is negligible), calculate according to the case when the driver transistor driver goes into cut-off and load transistor goes into saturation mode of operation. After application of derivation procedure for calculation propagation delay tppy, using load drain current and capacitive current during charge up, the propagation delay time for low-to-high output transition can be expressed as,

Fig. 3 The dependence of the output voltage critical value (Vo;), aS a function of the NMOS-load threshold voltage (Vio), when Vio,~= 0.5 V. Fig. 4 The dependence of the output voltage critical value (Vo,), as a function of the NMOS-driver threshold voltage (Vio.2), when Vio;= - 0.3 V. Fig. 4 The dependence of the output voltage critical value (Vo,), as a function of the NMOS-driver threshold voltage (Vio), when V,9;= - 0.3 V.

The presented results from Fig. 6 to Fig. 11 show that for higher absolute values of the NMOS-load transistor threshold voltage, as well as the higher value of the NMOS-driver transistor threshold voltage, the input critical voltage values (V;; and Vj) will have higher values, while for higher values of the NMOS transistors transconductance parameters ratio, the input critical voltage values will be lower, with more sensitivity in the low values band of the NMOS transconductance parameters ratio. NMQOS_inverter noice maroine far honth lagcic valtace

In Fig. 15, Fig. 16 and Fig. 17 is shown the influence of the NMOS transistor threshold voltage values and the NMOS transistors transconductance parameters ratio in VTC characteristic shape. From presented characteristics show that for lower absolute values of NMOS-load transistor threshold voltage, and for lower values of NMOS-driver ransistor threshold voltage, the VTC characteristic shift to the left, compared to the higher values and he slope of the VTC characteristic remains almost he same. While the value of NMOS transistors ransconductance parameter ratio increases, the slope of the VTC characteristic rise and shows better switchine nerformances.

Fig. 16 The VTC characteristic forms of NMOS inverter for some parametric values of the NMOS- Fig. 15 The VTC characteristic forms of NMOS inverter for some parametric values of the NMOS- load transistor threshold voltage, when: Vio, q = 0.5 V,k,=4, L=0.18 um, W= 1 wmand Vpp = 2.5 V.

Fig. 17 The VTC characteristic forms of NMOS inverter for some parametric values of NMOS transistors transconductance parameters ratio (k, = k Vk) when: Vio = 0.5 V, Viol =— 0.5 V, L=0.18 um, W= 1 um and Vpp = 2.5V.

Fig. 21 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-load transistor transconductance parameters (ky < kin < ky, or ky = 2k = 6ki;), when Vio. = - 0.4 V, Vop = 2.5 V and C,; = 12 pF. Fig. 20 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-load transistor transconductance parameters (ki < ki < ky, or ky = 2k = 6ki;), when Vio. =- 0.5 V, Vpp = 2.5 V and C; = 12 pF.

Fig. 22 Time response of output voltage in NMOS inverter on input driver voltage for some different values of NMOS-driver transistor transconductance parameters (ky < ka < kw, or kag = 2k = 10kq1), when Vio; = - 0.5 V, Vpp = 2.5 V and C, = 12 pF. Impact of Vio voltage of NMOS-driver transistor is significantly smaller in delay time tpy., compared with the impact the threshold voltage V,) of NMOS- load transistor in time delay tppy. Impact on the propagation delay time values will have also and source voltage values Vpp and equivalent capacitive load C, connected to the output of inverter (fan-out parameter).

Tab. 1 The operating regions and the voltage levels of the driver and load transistors at critical voltage values in NMOS inverter. NMOS transistors are constructed on the same substrate, therefore in NMOS transistor which acts as the load, the body effect must be taken in consideration [6, 7, 8, 9, 10, 11, 13]. Critical voltage values are determined using combinations of operation regions (operation modes) of NMOS-driver transistor and NMOS-load transistor, depending on the level of the output voltage values relative to the voltage values at the input of NMOS driver transistor (enhancement type NMOS). In Tab. 1 are shown the operating regions and the voltage levels of NMOS transistors in NMOS inverter for critical voltage values at the input of driver transistor.

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design

by Nebi Caka

2023

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo-NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

Fig. 1 The physical structure of an enhancement-type MOSFET (NMOS) in perspective view.

The pseudo-NMOS _ inverter contains two interconnected MOSFET transistors: one NMOS transistor (Qy) which works as driver and one PMOS-transistor (Qp) which works as an active load. The pseudo-NMOS inverter is shown in Fig. 2.

Fig. 3 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 1 V. Variation of the active load current (ipp) and the driver current (ipy) as function of output voltage (vo) for various values of the driver threshold voltage Qn), when the input voltage will have value of Vpp Vin = Vop, Vop = 3.3 V) and V ipo = — 0.4 V are represented in Fig. 3, Fig. 4, Fig. 5 and Fig. 6. During hese analyses the dimensions of NMOS and PMOS ransistors will be the same, while the ratio of the ransconductance process parameter (or device ransconductance parameter) will be kp = 4.

Fig. 4 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 0.7 V.

Fig. 5 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.5V.

Fig. 6 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Ving =0.2V.

Fig. 7 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the active load threshold voltage is Vipp =— 1 V. Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) for various values of active load threshold voltage (Vino), where the input voltage and driver threshold voltage will be held at constant values (Vi, = Vpp, Vino = 0.4 V) are represented in Fig. 7, Fig. 8, Fig. 9, Fig. 10.

Fig. 9 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vig =— 0.5 V. Fig. 8 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Ving =— 0.7 V.

Fig. 10 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vino =— 0.2 V. Based on accrued resultants for Fig. 7 to Fig. 10 it can be concluded that: the static current J,,.; when the output is at the low logic level, it depends on the values of the load threshold voltage, and results on he lower values for higher values of active load hreshold voltage, and also for higher values of load hreshold voltage the value at low-output state will be ower. Also in this case the values of static current Isat) and output voltage (Voz) will be disadvantages of pseudo-NMOS invertors for low-output state, which will have impact in the noise margin for low evel (NM,) and static power dissipation Pp as in Fig. 11.

The active load threshold voltage (PMOS) will have impact in propagation delays during the low to high transition (tpry). For two different values of the active load threshold voltage the low to high transition is represented in Fig. 13. Fig. 13 Time response of output voltage on input voltage when the active load threshold voltage

Fig. 12 The pseudo-NMOS inverter with capacitive load C, = 0.5 pF. The values of threshold voltage which characterize the driver transistor (NMOS) and active load transistor (PMOS) will have influence on propagation delays in pseudo-NMOS invertors. For the examine time delays it will be used a pseudo- NMOS inverter which drives a capacitive load C; of 0.5 pF as in Fig 12.

Fig. 14 Time response of output voltage for two periods of input voltage when the active load threshold voltage (PMOS) has two different values and the driver threshold voltage (NMOS) holds fixed value of Vin = 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vino = — 0.3 V, the V(VOUT2) curve corresponds to the output voltage when V9 =— 0.7 V. In Fig. 14 there are represented the shapes of output voltages for two periods of inputs voltages when the active load threshold voltage has two different values.

Fig. 15 Time response of output voltage on input voltage when the driver threshold voltage (NMOS) has two different values, and the active load threshold voltage (PMOS) holds fixed value of Vipo = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vi. = 0.7V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V. during high to low transition at output voltage (¢tpyz). In Fig. 15 it is shown the impact of the driver threshold voltage in propagation delays (tex) when two different values of driver threshold voltage are considered as parametric value.

Fig. 16 Time response of output voltage for two periods of input voltage when the driver threshold voltage (NMOS) has two different values and the active load threshold voltage (PMOS) holds fixed value of Ving = — 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vio = 0.7 V, the V(VOUT2) curve corresponds to the output voltage when V9 = 0.2 V.

Fig. 17 The waveforms of input and output voltages for two different values of capacitive load C;. The first case is when the capacitive load has value of C; = 0.5 pF, and second case is when load has value of C;, = 1 pF. The driver threshold voltage has two different values of 0.6V and 0.2V, whereas the active load threshold voltage has fixed value of — 0.7V.

Fig.18. Varation of the driver and active load current (Ion, Ipp) on output voltage (V,), when the input driver voltage is high (Vi, = Vpp) and the device transconductance parameters ratio has four parametric values: 4, 8, 12 and 16. The breakpoints between load curve (/p,) and driver current (/p,) will give the level values of Vor. The shape of the driver and active load currents, level value of static current and level value of low output state for some different values of device parameters ratio (kr) are shown in Fig. 18.

Fig.19 Input-output voltage transfer characteristic (VTC) of the pseudo-NMOS inverter, when the device transconductance parameter ratio has values of kr = 4, 8, 12 and 16. The variation of the VTC characteristic on kp as parametric values is shown in Fig. 19.

Fig. 20 Time response of output voltage on input voltage when the devices transconductance ratio has for different values of kp = 4, 8, 12, and 16.

Fig. 21 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Vi» = 0.7 V and active load threshold voltage is Ving = — 0.4 V. During the design phase of pseudo-NMOS logic circuits, designers must take into consideration the values of the threshold voltage of transistors which contain that logic gate. Firstly, it will begin with the VTC (voltage transfer characteristic) of pseudo- NMOS invertors and show its shape for the some different values of the driver threshold voltage where the load threshold voltage has same values as in Fig. 21 and Fig 22.

Fig. 22 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Ving = 0.2 V and active load threshold voltage is Vipgp =—0.4 V.

Fig. 23 NAND pseudo-NMOS gates with 4-inputs. In the static work regime, the values of driver threshold voltages will have impact on the value Vo,

Fig. 25 Shape of VTC-NAND gates for different number inputs (fan-in) when Vino = 0.2V. Fig. 24 Shape of VTC-NAND gates for different number inputs (fan-in) when V;,9= 0.7 V. Shape and slope of characteristics from Fig. 24 and Fig. 25 show that in the NAND gate fan-in has significant role and for higher values of number inputs (fan-in) there will be lower slope of VTC and higher values for low output state. The higher values of fan-in will result in higher values of propagation delays.

of NAND structure. The VTC-NAND shapes and values of Vo, for two different values of driver threshold voltage when fan-in has four different values are represented in Fig. 24 and Fig. 15.

Fig. 26 NOR pseudo-NMOS gates with 4-inputs.

Fig. 28 Shape of VTC NAND gates for different number inputs (fan-in) when Ving = 0.2V. Fig. 27 Shape of VTC NOR gate for different number inputs (fan-in) when V;,. = 0.7 V.

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Impact of MOSFET parameters on its parasitic capacitances

by Nebi Caka

2023, Proceedings of the 6th WSEAS …

Impact of MOSFET parameters on its parasitic capacitances NEBI CAKA, MILAIM ZABELI, MYZAFERE LIMANI, QAMIL KABASHI Faculty of Electrical and Computer Engineering University of Prishtina 10110 Prishtina, Fakulteti Teknik, Kodra e Diellit,... more

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A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

by HIMANSHI AWASTHI

2022, Silicon

This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs. The parabolic approximation equation... more

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Myzafere Limani

2022

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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Role of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static and switching conditions of operation

by Myzafere Limani

2022

The aim of this paper is to show the influence of the threshold voltage and transconductance parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static and switching conditions of operation, as well as... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS invertors

by Myzafere Limani

2022, WSEAS Transactions on …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits... more

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Impact of MOSFET parameters on its parasitic capacitances

by Myzafere Limani

2022, Proceedings of the 6th WSEAS …

Impact of MOSFET parameters on its parasitic capacitances NEBI CAKA, MILAIM ZABELI, MYZAFERE LIMANI, QAMIL KABASHI Faculty of Electrical and Computer Engineering University of Prishtina 10110 Prishtina, Fakulteti Teknik, Kodra e Diellit,... more

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Impact of MOSFET parameters on its parasitic capacitances

by Milaim Zabeli

2022

Abstract: The aim of this paper is to calculate the MOSFET parasitic capacitances, and then based on the results obtained we can further see the impact of MOSFET physical parameters on these parasitic capacitances. These capacitances have... more

Fig. 2 Lumped representation of the parasitic MOSFET capacitances.

Fig.3 The dependence of gate capacitive effect on area S for the different values of parameter tox.

Fig.5. Dependence of junction capacitance drain- body Cy, and W on parametrical values of Y and x; of drain region, for: Na = 2: 10° cm”, Np = 10° cm?, Na (sw) = 4:10'° em®?; V,; = 0 V and V)=—5 V. Fig. 5 shows the dependence of equivalent capacitance C,», from the width of drain regions (W) for parametrical length value(Y) and depth value (x;)) of drain.

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The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

by Milaim Zabeli

2022, Natural and Engineering Sciences

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition... more

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Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

by Milaim Zabeli

2022

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition... more

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The threshold voltage of MOSFET and its influence on digital circuits

by Milaim Zabeli

2022, Proceedings of the 7th WSEAS …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

Fig.14 The logic “1” transfer when one pass. transistor is driving another pass-transistor. Fig. 13 Waveforms of outputs voltages when two pass-transistors connected in series. Output voltage will reduce according to V, and propagation voltage will increase from stage to stage.

Fg. 12 Waveform of output voltage V, for logic “0” transfer with one pass-transistor, when Vip = 0.5 V.

_. eS EK PISA 1d to or a ee, Fig. 17 Variation of Vz, (minimum input voltage which can be interpreted as logic “1”) as function of threshold voltage V;.

Fig.10 The logic “1” transfer with an NMOS.

Key words: threshold voltage, MOSFET parameters, enhancement-type NMOS, impurities, thickness of oxid layer, doped density, short-channel, narrow-channel, voltage level, propagation delay, output voltage level. Fig.1 The physical structure of an n-channel enhancement-type MOSFET in perspective view. Abstract: The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic device which contain MOSFET transistors. The results obtained emphasize the impact of each single physical parameter on the total value of the threshold voltage. Moreover, all of these parameters will have significant and small impact on the threshold voltage. Hence, by adjusting the values of MOSFET physical parameters the accepted threshold voltage can be achieved. As the threshold voltage will have influence on critical voltage values which characterise MOSFET digital circuits and delays during transfer logic states, it must be taken into consideration during design phase of logic gates. 2 The threshold voltage on MOSFET- transistors 2.1 The threshold voltage of NMOS The value of the gate-to-source voltage Vas needed to create (induced) the conducting channel (to cause surface inversion) is called the threshold voltage (V;, or V,). The value of the threshold voltage is dependent from some physical parameters which characterize the MOSFET structure such as: the gate material, the thickness of oxide layer ¢,,, substrate doping concentration (density) Ny, oxide—interface fixed charge concentration (density) N,,, channel length L, channel width W and the bias voltage Vsg [1, 2, 5].

Fig.3. The dependence of the threshold voltage Vin on thickness of oxide layer ¢,, for parametric values of substrate doping density Ny, when N,, = 2*10'° cm”. Fig.2. The dependence of the threshold voltage Vio on thickness of oxide layer ¢,, for parametric values of oxide-interface fixed charge density N,,, when Ny = 10'° cm®.

2.2. The threshold voltage of NMOS transistors with short-channel

Fig.6 Simplified geometry of the MOSFET channel region. Close-up view of the drain diffusion edge.

(Vps) on the voltage term AV,o, are shown in Fig.7, Fig.8. Fig.7 The dependence of the AViy on the length Z for parametric values of depth x;, when Ny = 10'° cm?, Np = 10" em®, ty, = 20 nm and Vps = OV.

Fig.11 The reduction of output voltage level by threshold voltage, when V,=0.5V.

Fig.15 Waveform of output voltage V, for logic “1” transfer, when each pass-transistor (NMOS) is driving another pass-transistor (NMOS) and Vg = 0.5V.

are represented in below diagrams (for supply voltage Vpp = 3.3 V) Fig. 16, Fig. 17, Fig. 18.

The voltage value V;, will increase for higher value of threshold, while Vj; will decrease for higher value of threshold voltage. The noise margins (NM) for two levels will increase.

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Impact of MOSFET parameters on its parasitic capacitances

by Milaim Zabeli

2022, Proceedings of the 6th WSEAS …

Impact of MOSFET parameters on its parasitic capacitances NEBI CAKA, MILAIM ZABELI, MYZAFERE LIMANI, QAMIL KABASHI Faculty of Electrical and Computer Engineering University of Prishtina 10110 Prishtina, Fakulteti Teknik, Kodra e Diellit,... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS invertors

by Milaim Zabeli

2022, WSEAS Transactions on …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits... more

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The impact of MOSFET's physical parameters on its threshold voltage

by Milaim Zabeli

2022, Proceedings of the 6th …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold... more

Key words: MOSFET parameters, threshold voltage, body effect, enhancement-type NMOS, doped density, short: channel, narrow-channel. Fig.1 The physical structure of an n-channel enhancement-type MOSFET: (a) perspective view; (b) cross-section. Abstract: The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold voltage. The MOSFET threshold voltage value will have influence in the dynamic and static work regime (mode) of device. Based on the results obtained we can further see impact of each single physical parameter on the total value of threshold voltage. Moreover we can see which of these parameters will have significant and small impact on the threshold voltage. Hence, considering we can adjust the values of MOSFET physical parameters to reach the accepted threshold voltage.

From Fig.2 and Fig.3, based on acquired values we can see influence of ¢,,, N, and N,, in values of threshold voltage. For larger value of each parameter: tox, or Ny the value of threshold voltage will increase.

Fig.5 (a) Simplified geometry of the MOSFET channel region, with gate-induced bulk depletion region and the pn-junction depletion regions. (b) Close-up view of the drain diffusion edge. -Xas, Xap Tepresent the depth of depletion regions at source and drain as results of pn junction, respectively.

Fig.7 The dependence of the AVio on Np (source and drain doping density), when Na=10'°cm”, L=1ym, tox=20nm, xj=lum and Vps=0V.

Fig.6 The dependence of the AV; on the length Z for parametric values of depth x;, when N, = 10'° cm”, Np = 10'* cm”, t,, = 20 nm and Vps = OV.

The voltage term AV, as results of narrow-effects if shapes of the depletion region edges are modeled by quarter-circular arcs can be found as [2]:

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Dynamic and Channel Adaptive Error Control Scheme in Wireless Sensor Networks

by Rajashekhar Biradar

2022

The application of wireless technology is increasingly influencing the deployment of sensor networks at low cost and maintainance in all walks of life. Poor channel conditions, severe power constraints, fading, interference and the low... more

Usually, the received signal can no longer be modeled as a determinis noise (WGN). Instead, it ic signal in white Gaussian should be considered as a function of either the state of a Markov chain or of its state transition probabili observed in the WGN. Mar stochastic process where t depends only on the prese y with known parameters kov chain is a special kind of he outcome of an experiment nt state not on the preceding states. Markov chain is defined as the process with Figure 1: Channel adaptive error control scheme As shown in the figure 1, channel condition is estimated and the derived BER is divided into three ranges: lower, middle and higher. Depending on the BER range, error control scheme uses three modes to handle the erors. All the three modes are detailed in the figure. We have assumed low range of BER is from 10-9 to 10-12, mid range from 10-6 to 10-8 and high range from 10-3 to 10—5. For the low range, simple error control scheme without retransmission is used. For the middle range, error control scheme with retransmission is employed and for the high range, the error control is left to the upper layer. As BER depends on the SNR, its requirement is different for different services and systems. For instance, wireless link BER is less than 10—6 while optical BER is less than 10—12. On optical fiber link, the average BER is approximately 10—9 where as on a coaxial cable, the probability of bit errors is around 10—6. For a switched telephone line, these numbers are even higher between 10—4 and 10—5. Digitized voice can tolerate bit errors as high as 1 bit per thousand bits sent i.e 10-3. Computer data requires a BER of 10—6 to 10-12 (i.e. 1 per million to 1 per trillion) depending on the content.

Figure 3: Markov chain representation of errors where s is the number of states in the Markov chain and p is the transition probability from current to next state where as (1— p) is the probability to remain in the same state. Using these transition probabilities, one can establish an asymptotic formula for the capacity of a BSC as the noise parameter tends to zero. To capture the bursty nature of wireless networks, Markov chains have been extensively used to model the error sequences generated by a wireless channel where a BSC is associated with each state. TheMarkov chain provides a good approximation of the error process in fading channels. Here, the Markov state and transition probabilities between the states are assumed. As shown in the figure 3, the probability pj (n) = P(Xn = }) is the probability of the system to reach state j inn steps. For instance, p2(1) = P(X1 = 2) is the probability to reach state 2 from state 1 in one step. The channel states associated with consecutive symbols are assumed to be the neighboring states for a slow fading channel where the SNR varies slowly as the symbol interval T increases. Each state describes the SNR level received as the interval T increases. In order to estimate the errors, we need to find out the expression for BER in terms of SNR using the standard deviation and mean. To estimate the BER, the system should move from one state to another in both the directions from good to bad and vice versa. The type of random noise in a communication system that determines the BER of a circuit is the thermal noise which can well be described by additive white Gaussian (AWG) noise across a narrow frequency band. Even though it is possible to have other types of noise from the interfering signals that combine with thermal noise in the final BER, the type of noise addressed here is purely Gaussian. where Cb is Boltzmann’s constant and Ttotal is system noise temperature in Kelvin. Note that Ttota the sum of all the individual noise temperatures in he previous gains in the system system normalized by t The Gaussian distributi to detect an observed standard deviation of probability of a signal being misinterpreted (or in error) by the system, one just needs to know the number standard deviations tha average signal level so that the signal can cross threshold value. The equation 3 on provides with the probabi value given the mean and he measurement. To know is added or subtracted from he is he ity he he of he he n this number of standard deviations is related to the probability, (P) of an error occurring, using the Gaussian function as shown in

net eg ee ee Ee As shown in the figure 6, the throughput fluctuates for various SNR values for a fixed number of frame lengths. However the throughput increases as the SNR increases. This is because, as the SNR increases, the number of errors in the frame decreases thereby Figure 6: Throughput Vs.SNR increasing the number of frames delivered thus increasing the throughput. The throughput is. slightly more for DCAECS compared to ASAEC since in the case of ASAEC, the throughput increases with SNR slowly. In case of DCAECS, the throughput increases fast with various SNR values.

Figure 7: Probability of Errors Vs. Number of Errors for different message lengths plotted against frame lengths for different values of BER. As the frame length increases, the PRTx also increases slowly and remains constant at some point (L = 200bits). This plot indicates that PRTx initially increases and later remains stable as the frame length increases.

as a Pees Wee TEESE RAST SA) era’ She Although ASAEC “speaks about ARQ, it does not analyze the probability of retransmissions where as DCAECS discusses about probability retransmission for different frame lengths. As shown in the graph in figure figure 8, the probability of retransmission is PRTXx is

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Dynamic and Channel Adaptive Error Control Scheme in Wireless Sensor Networks

by Mallanagouda Patil

2022

The application of wireless technology is increasingly influencing the deployment of sensor networks at low cost and maintainance in all walks of life. Poor channel conditions, severe power constraints, fading, interference and the low... more

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Fast and accurate statistical characterization of standard cell libraries

by Philippe J . Roussel

2022, Microelectronics Reliability

With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of... more

Fig. 1. Compact variability modeling: (a) using simulator capability on instantia- tion; (b) voltage source modeling variations in Vt; and (c) voltage source modeling variations in Vt and current source modeling variations in the current gain Af/f.

Fig. 2. (a) Traditional Monte Carlo flow; (b) error propagation using linear sensitivity analysis and (c) proposed flow based on DoE and RSM. Brussel design of experiments is a pre-processing step to deter- mine a small set of Ngoe artificially generated points representing the original sample of N random AVt and Af. Then a model selec- tion algorithm finds the optimal non-linear regression model relat- ing inputs to outputs. Finally, a large sample of MC experiments can be run using the surrogate model instead of spice. If these assumptions hold then the output of the simulation (de- lay for instance) can be approximated as a Normal random vari- able, and its moments can be computed analytically. The inputs for the commercial tool performing sensitivity analysis are the standard deviations of the inputs (oy, and o,; of each transistor i). The tool then gives as outputs 1) the nominal simulation s and 2) the sensitivities of each response (delay, transition) to each in- put parameter, €.g. Syri, Ss; Which are computed numerically using a first order Taylor series expansion:

Fig. 3. Upper-right diagonal: pairwise 2-D distributions and histograms of Vt and f of an inverter. Brussel DoE points are the large squares. Diagonal: histograms of Vt and f. Lower diagonal: correlation coefficients.

Fig. 4. Distribution of residuals of the full linear fit and the non-linear fit with quadratic and cross-terms of the FF. The residuals of the non-linear model are smaller and the distribution is closer to a Normal distribution.

Fig. 5. Quantile-quantile plot (normal distribution is a straight line) of the distribution of FF setup time comparing true response computed using MC with linear sensitivity analysis (EP) and RSM. Inset shows histogram and PDFs. In this section we compare the response distributions obtained using the proposed methodology with the one given by the com- mercial tool and the one obtained by MC. Figs. 5-7 present, respec- tively, the distributions of setup time, hold time and clock-to-q delay of the flip-flop cell (FF). In the insets, these figures show the histogram of MC (reference), as well as curves representing the PDFs obtained using MC analysis and the non-linear RSM. Lin- ear sensitivity analysis and the RSM present good agreement with MC. Nevertheless, combined PDF or histogram graphs on a linear scale lacks visual information about the accuracy on the tails. For analysis of the distribution with sufficient accuracy this work uses Quantile-Quantile (Q-Q) Plot, very widespread amongst the Statis- tic community. These figures show Q-Q plots of the hold time, set- up time and clk-to-q delay distributions. Using this technique allows us to verify that the non-linear method has a perfect agree- ment with MC simulations on the whole domain of the distribu- tion: both in the center and the tails. On the other hand, the

Fig. 6. Q-Q plot of the FF hold time comparing true response computed using MC with linear sensitivity analysis (EP) and RSM. Inset shows histogram and PDFs.

Fig. 8. Error of linear sensitivity and RSM approaches as compared to Monte Carlc using 1000 runs. Fig. 7. Q—-Q plot of the FF clock-to-q delay comparing true response computed using MC with linear sensitivity analysis (EP) and RSM. Inset shows histogram and PDFs.

Benchmark of std cell library generated using our methodology as compared to Monte Carlo. Please cite this article in press as: Brusamarello L et al. Fast and accurate statistical characterization of standard cell libraries. Microelectron Reliab (20 doi:10.1016/j.microrel.2011.05.016 Table 1

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Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

by Myzafere Limani

2022

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition... more

the subthreshold conductions and leakage currents are neglected [7,12-15]. Figure 1. The structure of the CMOS inverter which contains two complementary enhancement-type MOS a ee transistor drives (pulls up) the output node while the NMOS acts as load [6,7,12].

Figure 2. The typical VTC of the CMOS inverter.

Figure 3. The dependence of input voltage critical value Vi on ratio of MOS transistor transconductance

Figure 4. The dependence of input voltage critical value Vz on the ratio of MOS transistor transconductance parameters kr for two different values of PMOS threshold voltage (Vioy), when threshold voltage of NMOS transistor has constant value of Vion = 0.5V. Figure 4. The dependence of input voltage critical value Vi on the ratio of MOS transistor transconductance

Figure 5. Influence of MOS transistor transconductance parameters ratio (kr) on output voltage value Vo, when the input terminal of CMOS inverter is biased by voltage Vi = Vu, for several parametric values of complementary MOS transistor threshold voltage. Figure 5. Influence of MOS transistor transconductance parameters ratio (kr) on output voltage value Vo, wher From the results presented in Figures 3 and 4 for the input voltage critical value Vi, we note that

Figure 6. The dependence of the voltage critical value Vix on MOS transistors transconductance parameters ratio remains constant Vio» = - 0.5 V.

Figure 7. The dependence of voltage critical value Viz on MOS transistors transconductance parameters ratio kr

Figure 8. The impact of the transconductance parameters ratio (kr) of MOS transistors (NMOS and PMOS) o1 values of complementary MOS transistors threshold voltage (NMOS and PMOS threshold voltage) different values of the NMOS threshold voltage, when Viop = - 0.5 V and source voltage Vpp = 2.5 V.

Figure 10. The dependence of the noise margins for low logic level NMt on complementary MOS transistors transconductance parameters ratio kr, for three cases of different MOS transistor threshold voltage (NMOS and PMOS transistors), when Vop = 2.5 V. Figure 10. The dependence of the noise margins for low logic level NM on complementary MOS transistors voltages in both logic levels are shown in Figures 10 and 11. “ The immunity of CMOS inverter on unwanted signals is expressed through the noise margins for both logical levels (for low level and for high level). The parameters that characterize the complementary MOS transistors in a CMOS inverter determine the noise margins level for both logical levels. The dependence of noise margins (NM) on the complementary MOS transistors transconductance parameters ratio, for several parametric values of MOS transistors threshold voltages in both logic levels are shown in Figures 10 and 11. transconductance parameters ratio, for several parametric values of MOS transistors threshold logical levels. The dependence of noise margins (NM) on the complementary MOS transistors

Figure 11. The dependence of the noise margins for high logic level NMu on complementary MOS transistors threshold voltage, the noise margin for high level NMH will increase especially in the range of higher

Figure 12. The impact of complementary MOS transistors channel length ratio (W/W ,) on VTC shape, when Ln = Lp, Vion = | Viop|=0.5 V and Vop = 2.5 V.

Figure 13. The impact of the NMOS transistor threshold voltage (Vion) on VTC shape, when PMOS transistor threshold voltage is Viop = - 0.5V, and transistors have identical dimensions. Figure 13. The impact of the NMOS transistor threshold voltage (Vion) on VTC shape, when PMOS transistor from the lower value of the NMOS threshold voltage (Vion), which is reflected in the voltage critical threshold voltage remains unchanged, the VTC characteristic of CMOS inverter shall shift to the right

Figure 14. The impact of PMOS transistor threshold voltage (Vioy) on CMOS inverter VTC shape, when NMOS transistor threshold voltage value is Vion = 0.5 V, and transistors have identical dimensions. Figure 14. The impact of PMOS transistor threshold voltage (Vioy) on CMOS inverter VTC shape, when NMOS

Table 1. Operation modes of complementary MOS transistors (NMOS and PMOS transistors) The characteristic properties that characterize the VTC characteristic are some voltage critical values at the input and output terminal of the CMOS inverter, as: Vou, Vou, Vit, Vin, Vin [3], [4]. the various ratios of the input voltage levels and the output voltage levels. Operation modes of

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The impact of MOSFET's physical parameters on its threshold voltage

by Qamil Kabashi

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold... more

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Impact of MOSFET parameters on its parasitic capacitances

by Qamil Kabashi

2021

The aim of this paper is to calculate the MOSFET parasitic capacitances, and then based on the results obtained we can further see the impact of MOSFET physical parameters on these parasitic capacitances. These capacitances have a direct... more

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The threshold voltage of MOSFET and its influence on digital circuits

by Qamil Kabashi

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS inverters

by Qamil Kabashi

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits... more

Influence of the length channel LZ, the depth x; of drain (source) regions and drain-to-source voltage (Vps) on the voltage term AVjo, are shown in Fig.7, Fig.8.

“ig.10 The logic “1” transfer with an NMOS. The MOS transistors in pass- transistor logic circuits used to transfer logic state between input and output nodes. During logic “1” transfer and “0” transfer the threshold voltage will have impact on level of output voltage and delay times. In Fig.10 is illustrated the logic “1” transfer with an NMOS.

Fig.13 The reduction of high output voltage level by threshold voltage (“poor 1”), when Vi9=1V. Fig.12 The reduction of high output voltage level by threshold voltage (“poor 1”), when Vy=0.6V.

Fig.11 The reduction of high output voltage level (Von) by threshold voltage (“poor 1”), when Vg=0.2V.

Fg. 14 Waveform of output voltage V, for logic “0” transfer with one pass-transistor, when V)=0.2V.

Fg. 15 Waveform of output voltage V, for logic “( transfer with one pass-transistor, when V,)=0.6V.

Fig. 18 Three identical pass-transistors connected in series. Now consider the following case in which will have three identical pass-transistors connected in series (in cascades) as in Fig. 18.

Fig. 19 Waveforms of outputs voltages when three pass-transistors connected in series, when V{9=0.6V.

Fig. 20 The logic “1” transfers when one pass- transistor is driving another pass-transistor (node voltages during the “1” transfer).

Fig.21 Waveform of outputs voltages V, for logic “1” transfer, when each pass-transistor (NMOS) is driving another pass-transistor (NMOS) and Vig = 0.6V.

The threshold voltage will have influence on critical voltages values which characterize MOS inverters and voltage transfer characteristic. The impact of V; on critical voltages values for a symmetric CMOS inverters are represented in below diagrams (for supply voltage Vpp=3.3V) Fig. 22, Fig. 23, Fig. 24 and Fig. 25.

Fig. 23 Variation of Viy (minimum input voltage which can be interpreted as logic “1”) as function of the threshold voltage V;. In symmetric case on CMOS inverters the noise margins for two levels are equal NM; =NMy.

Fig. 25 Variation of propagation delay tp as function of the threshold voltage V; 3.3 Influence of threshold voltage on critical voltage values and delay times in pseudo- NMOS inverters

Fig. 28 Variation the Vin of pseudo-NMOS inverter as function of the threshold voltage Fig. 27 Variation of the Vj, of pseudo-NMOS inverter as function of the threshold voltage V,.

Fig. 26 Variation of the threshold voltage of pseudo- NMOS inverter (Vm) as function of the threshold voltage V,..

Fig. 29 Variation of the Vo, of pseudo-NMOS inverter as function of the threshold voltage V,.

Fig. 32 Variation the les of pseudo-NMOS inverter as function of the threshold voltage

Fig. 1 The physical structure of an n-channel enhancement-type MOSFET in perspective view. Key words: Threshold Voltage, MOSFET Parameters, Enhancement-Type NMOS, Impurities, Doped Density, Short-Channel, Narrow-Channel, Voltage Level, Propagation Delay, Critical Values. The value of the gate-to-source voltage Vas needed to create (induced) the conducting channel (to cause surface inversion) is called the threshold voltage (Vi, or V;). The value of the threshold voltage is dependent from some physical parameters which characterize the MOSFET structure such as: the gate material, the thickness of oxide layer ¢,,, substrate doping concentrations (density) N4, oxide—interface fixed charge concentrations (density) N,,, channel length L, channel width W and the bias voltage Voz [1, 2, 5]. Abstract: The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits that contain the MOSFET transistors. The results obtained emphasize the impact of each single physical parameter on the total value of the threshold voltage. By adjusting the values of MOSFET physical parameters the accepted threshold voltage can be achieved. Since the threshold voltage will have influence on critical voltage values which characterise MOS inverters and delay times during transfer logic states between stages, it must be taken into consideration during design phase of logic gates that contain the MOSFET transistors. 2 The threshold voltage on MOSFET- transistors 2.1 The threshold voltage of NMOS- transistors with long-channel

Fig. 3 The dependence of the threshold voltage Vig on thickness of oxide layer t,, for parametric values of substrate doping density Ny, when N,, = 2*10'°cm?.

Fig.5 shows the dependence of the threshold voltage Vo on extra p-type impurities which is added into the channel region.

Fig.7 The dependence of the AViy on the length ZL for parametric values of depth x, when Ny = 10'° cm”, Np = 10" cm®, t,, = 20 nm and Vps = OV.

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design

by Qamil Kabashi

2021

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo- NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Qamil Kabashi

2021

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

by Qamil Kabashi

2021

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition... more

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Influence of MOSFET parameters on its parasitic capacitance and their impact in digital circuits

by Myzafere Limani

2021, WSEAS Transactions on Circuits and Systems

Advanced development of technological processes influenced a wide use of MOSFET transistors in design of integrated digital circuits with high density packages (VLSI). However, in MOSFET transistors parasitic capacitances are present,... more

Fig. 2 Lumped representation of the parasitic MOSFET capacitances. Fig. 1 Cross-section view and the top view of typical n-channel MOSFET.

Fig. 3 Three-dimensional view of the n* diffusion regions within the p-type substrate. In the sidewalls 2, 3 and 4 p* regions we usually have density about 10N,. In practice the actual region shape is quite complicated and impurity concentration is not uniform.

In Fig. 4 is shown the dependence of gate capacitive effect in the so-called “worst case” conditions on area S (product between width and length channel), for parametric values of thickness of oxide layers (t,,). With the so-called “‘worst case” we understand the case when gate capacitive effect reaches its maximal value.

Fig. 6 Dependence of junction capacitance drain- body Cq and W on parametrical values of Y of drain region, for: x, = 0.4 ym, Ny =4-10'° cm®, Np =2-10"° cm®, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.

Fig. 7 Dependence of junction capacitance drain- body Ca, and W on parametrical values of Y of drain region, for x, = 0.8 ym, Ny =4-10 cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm*; V; =0 V and V. =—5V.

Fig. 8 Dependence of junction capacitance drain- body Ca and W on parametrical values of Y of drain region, for x; = lym, Na = 4:10" cm®, Np = 2-10" cm?, Na (sw) =4:10'° cm; V; =OV and V2 =—5V.

To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, firstly we consider the depletion region thickness, which is xg. Assuming that the n-type and p-type doping densities are given by Np and Na, respectively, and that reverse bias voltage is given by V (negative), the depletion region thickness can be calculated as [3, 5]:

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Myzafere Limani

2021

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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Role of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static and switching conditions of operation

by Myzafere Limani

2021

The aim of this paper is to show the influence of the threshold voltage and transconductance parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static and switching conditions of operation, as well as... more

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Influence of the driver and active load threshold voltage in design of pseudo-NMOS logic

by Myzafere Limani

2021

During the design phase of different logic gates based on MOS technologies, it is necessary to take into consideration many parameters which characterise MOS transistors. One of the parameters which characterizes all types of MOSFET... more

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design

by Myzafere Limani

2021

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo-NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

The pseudo-NMOS inverter contains two interconnected MOSFET transistors: one NMOS transistor (Qx) which works as driver and one PMOS-transistor (Qp) which works as an active load. The pseudo-NMOS inverter is shown in Fig. 2.

Fig. 6 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of driver is Vino = 0.2V.

Fig. 9 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load 1s Vig =— 0.5 V. Fig. 8 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Ving =— 0.7 V.

Fig. 10 Variation of load (ipp) and driver (ipy) current as function of output voltage (Vo) when the threshold voltage of active load is Vio =— 0.2 V. Based on accrued resultants for Fig. 7 to Fig. 10 it can be concluded that: the static current J,,.; when the output is at the low logic level, it depends on the values of the load threshold voltage, and results on he lower values for higher values of active load hreshold voltage, and also for higher values of load hreshold voltage the value at low-output state will be ower. Also in this case the values of static current Isat) and output voltage (Voz) will be disadvantages of pseudo-NMOS invertors for low-output state, which will have impact in the noise margin for low evel (NM,) and static power dissipation Pp as in Fig. 11.

The active load threshold voltage (PMOS) will have impact in propagation delays during the low to high transition (tp_y). For two different values of the active load threshold voltage the low to high transition is represented in Fig. 13. Fig. 13 Time response of output voltage on input voltage when the active load threshold voltage

Fig. 14 lime response of output voltage for two periods of input voltage when the active load threshold voltage (PMOS) has two different values and the driver threshold voltage (NMOS) holds fixed value of Vin = 0.7 V. The V(VOUT1) curve corresponds to the output voltage when Vino = — 0.3 V, the V(VOUT2) curve corresponds to the output voltage when V5) =— 0.7 V. In Fig. 14 there are represented the shapes of output voltages for two periods of inputs voltages when the active load threshold voltage has two different values.

Fig.18. Varation of the driver and active load current (Ion, Ipp) on output voltage (V,), when the input driver voltage is high (V;, = Vpp) and the device transconductance parameters ratio has four parametric values: 4, 8, 12 and 16. The breakpoints between load curve (/p,) and driver current (/p,) will give the level values of Vor. The shape of the driver and active load currents, level value of static current and level value of low output state for some different values of device parameters ratio (kr) are shown in Fig. 18.

Fig. 21 Shape of VTC for pseudo-NMOS inverter when the driver threshold voltage is Ving = 0.7 V and active load threshold voltage is Ving = — 0.4 V. During the design phase of pseudo-NMOS logic circuits, designers must take into consideration the values of the threshold voltage of transistors which contain that logic gate. Firstly, it will begin with the VTC (voltage transfer characteristic) of pseudo- NMOS invertors and show its shape for the some different values of the driver threshold voltage where the load threshold voltage has same values as in Fig. 21 and Fig 22.

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The threshold voltage of MOSFET and its influence on digital circuits

by Myzafere Limani

2021, Proceedings of the 7th WSEAS …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

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The impact of MOSFET's physical parameters on its threshold voltage

by Myzafere Limani

2021, Proceedings of the 6th …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold... more

Fig.6 The dependence of the AV, on the length L for parametric values of depth x;, when N, = 10'° cm”, Np = 10'* cm”, t,, = 20 nm and Vps = OV.

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Myzafere Limani

2021

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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The impact of MOSFET’s physical parameters on its threshold voltage

by Myzafere Limani

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It is also analysed the role of substrate (the body effect) on the threshold... more

descriptionView Paper arrow_downwardDownload

The threshold voltage of MOSFET and its influence on digital circuits

by Myzafere Limani

2021

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic

by Myzafere Limani

2021

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo-NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

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Influence of the driver and active load threshold voltage in design of pseudo-NMOS logic

by Myzafere Limani

2021

During the design phase of different logic gates based on MOS technologies, it is necessary to take into consideration many parameters which characterise MOS transistors. One of the parameters which characterizes all types of MOSFET... more

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Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

by Milaim Zabeli

2021

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition... more

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Impact of the threshold voltage and transconductance parameters of NMOS transistors in NMOS inverter performance for static conditions of operation

by Milaim Zabeli

2021

The objective of this paper is to show the influence of the parameters that characterize the NMOS transistors on the behavior of NMOS inverters in static operation mode, as well as set directive that should be followed during the design... more

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Influence of the driver and active load threshold voltage in design of pseudo-NMOS logic

by Milaim Zabeli

2021

During the design phase of different logic gates based on MOS technologies, it is necessary to take into consideration many parameters which characterise MOS transistors. One of the parameters which characterizes all types of MOSFET... more

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Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design

by Milaim Zabeli

2021

The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo-NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS... more

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The threshold voltage of MOSFET and its influence on digital circuits

by Milaim Zabeli

2021, Proceedings of the 7th WSEAS …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. The MOSFET threshold voltage value will have influence in behaviour of electronic... more

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Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS invertors

by Milaim Zabeli

2021, WSEAS Transactions on …

The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits... more

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MOSFET parameters

Key research themes

1. How do gate and channel engineering techniques mitigate short-channel effects and enhance performance in multigate MOSFETs?

2. What are the challenges and methods for accurate extraction and modeling of MOSFET intrinsic parameters, including source/drain series resistances and parasitic capacitances, for device and circuit simulations?

3. How do MOSFET device scaling and alternative materials like III-V semiconductors and 2D materials influence electrical parameters and technology scalability?

All papers in MOSFET parameters

MOSFET parameters

Key research themes

1. How do gate and channel engineering techniques mitigate short-channel effects and enhance performance in multigate MOSFETs?

2. What are the challenges and methods for accurate extraction and modeling of MOSFET intrinsic parameters, including source/drain series resistances and parasitic capacitances, for device and circuit simulations?

3. How do MOSFET device scaling and alternative materials like III-V semiconductors and 2D materials influence electrical parameters and technology scalability?

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All papers in MOSFET parameters