MOSFET compact modeling

The semiconductor devices industry is one of the most significant sectors, based on its broad applications and substantial economic and strategic implications. This article overviews the emerging technologies in transistor manufacturing processes, materials, and architectures. It discusses the latest trends in photo-lithography processes, focusing on extreme ultraviolet (EUV) lithography; at the transistor architectural level, the article discusses various transistor types, emphasizing fin field-effect transistor (FinFET) structure and properties. The article also briefs the latest semiconductor developing road map, promises, and challenges toward keeping up with Moore's integration rate.

Sequence detection is a fundamental operation in digital systems, commonly employed in communication protocols, pattern recognition, and error detection. Finite State Machines (FSMs) offer an efficient means of implementing sequence detectors due to their ability to process input streams systematically. This paper presents the design and implementation of a 101-sequence detector using non-overlapping mealy state machine FSMs, specifically leveraging the Mealy and Moore machine models. The sequence detector is implemented using Verilog HDL and simulated in open-source EDA Playground platform to validate its performance. The design methodology involves state diagram formulation, state transition tables, Karnaugh maps for optimization, and logic synthesis. Results confirm the accuracy and efficiency of FSM-based sequence detection, reinforcing its significance in real-time digital applications.

The voltage transfer characteristics (VTC) of a complementary metal-oxide-semiconductor (CMOS) inverter provides necessary information about some of the most important performance parameters, such as noise margin (low/high), inverter logic threshold voltage, and so on. Over years, there has been an increasing trend to use various commercially available Technology Computer Aided Design (TCAD) tools and circuit simulators to study such performance parameters. The emergence of novel devices has forced the theoretical research community to refine TCAD tools and simulators. We have developed a simulator that can plot the VTC curve of strained/unstrained nanoscale MOSFET based CMOS circuits. Our algorithm can faithfully reproduce the VTC curve of nanoscale MOSFET based CMOS inverter with an average deviation of less than 2%. We have also shown the dependence of VTC curves of nanoscale strained Si/SiGe and multi channel (MC)gate-all-around (GAA) MOSFET based CMOS inverters on some important device parameters.

As one of the important technological boosters, strain in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) was first introduced in the 90 nm node and it has been continuing since then. Incorporating strain in MOSFETs allow us to increase the performance of the device without appreciable scaling of the devices. However, the presence of Source(S)/Drain(D) series resistance may degrade the performance of strained MOSFETs in the nanometer regime. Theoretical research emphasizing on the modeling and analysis of the drain current and threshold voltage of nanoscale strained MOSFETs (NSM) needs to incorporate the S/D series resistance in order to get a better insight of such devices. In this paper we have carried out a systematic analysis of drain current and threshold voltage of nanoscale strained Si/SiGe MOSFETs through a multi-iterative technique taking into account the effects of S/D series resistance. Our analysis has been further extended to study the impact of some important parameters such as strained Si layer thickness, gate oxide thickness, Ge mole fraction, and so on, on the electrical parameters of NSMs. The scaling trend of some device parameters have been modeled by analytical expressions obtained through curve-fitting technique and have been incorporated in our analysis to obtain optimized performance of NSMs.

Owing to the persisting technological importance of Strained-Si (S-Si) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) and the hurdles offered by source (S) and drain (D) series resistances in the nanometer regime, a simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters. The algorithms used for framing the simulator are based on analytical equations which can accurately estimate the noise margin (NM), dynamic current, and so on. The effects of strain on the circuit performance have also been investigated, with emphasis on the variations of drain current dependent transconductance ratio. A scope of using high-k dielectric materials along with strain is also explored. The algorithms proposed in this work are not only restricted to strained-Si MOSFETs but can also be applied to any novel device structure and complex digital logics, presented as case studies.

Considering the fabrication difficulty of the highpermittivity (Hk) MOSFETs, this study proposes two aspect ratios, AR S for the n-pillars and AR I for the Hk-pillars, to optimize the specific on-resistance (R on,sp) under breakdown voltage of 1000 V. Numerical calculations by MATLAB and simulations by MEDICI demonstrate and validate that with sufficiently large permittivity ratios (K r) and optimal AR I , Hk MOSFETs can achieve lower R on,sp compared to conventional superjunction (SJ) MOSFETs. The accurate fitting function can be used to providing design instructions efficiently to make tradeoffs between fabrication difficulty and required R on,sp and BV.

A proposed optimization for high-k superjunction (H𝑘-SJ) MOSFETs focuses on reducing specific ON-resistance (R on,sp) in drift regions for three dimensional (3D) configurations in two cases (3DH𝑘core and 3DH𝑘shell) compared to 3D conventional SJ (C-SJ) and two dimensional Hk-SJ (2DH𝑘). Under constraints of avalanche breakdown and critical depletion, the optimized R on,sp and design parameters are determined. 3DH𝑘core achieves the lowest R on,sp of 12.43 mΩ cm 2 at 800 V breakdown voltage (BV) for small aspect ratios (AR) due to the lower breakdown electric field (𝐸-field) and impact ionization integral value, while 3DH𝑘shell excels 3DH𝑘core and 2DH𝑘 with a lower R on,sp of 6.395 mΩ cm 2 at large AR. Comparative research containing charge imbalance, temperature robustness, and switching characteristics is discussed after optimization. Taylor modeling for 3DH𝑘shell optimization is also proposed. For further manufacturing guidance, fitting and boundary curves formulas are provided.

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson's equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

We present the latest developments and some preliminary results on High-Voltage MOSFET modelling at EPFL. A novel physics-based compact model is derived for the drift region. It includes velocity saturation and Poisson equation in a self consistent formalism. Next, this drift extension has been combined with a non-uniformly doped MOSFET compact model for the low voltage section of the device. The complete model has been implemented in Verilog-A language. Evaluation against TCAD simulations and actual measurements on state-of-art HV-MOS devices confirm the soundness of this approach.

This paper presents the foundations that lead to the EKV MOS transistor compact model. It describes all the basic concepts required to derive the large-signal and smallsignal charge-based model that is valid in all modes of inversion, from weak to strong inversion through moderate inversion. The general small-signal model valid in quasistatic and non-quasi-static operation is also presented and all its components are described. It is also shown that the charge-based approach allows to derive the g m /I D characteristic that is valid in all modes of inversion.

The EKV 3.0 compact MOS transistor model for advanced IC design is presented. Its basis is an ideal analytical charge-based model including static to non-quasistatic dynamic aspects and noise. The ideal model is extended to account for the major second-order effects in deep-submicron CMOS technologies resulting from technology scaling and from short-channel effects. It is shown how these nonidealities affect the ideal device characteristics. The increasingly important moderate and weak inversion operation are emphasized. The hierarchical structure of the model is presented, essential features and effects are outlined and illustrated with respect to device characteristics in deepsubmicron CMOS.

The MOS transistor drain current is the (linear) superposition of independent and symmetrical effects of source and drain voltages. This basic property is not affected by the geometry or symmetry of the transistor, by the level of gate voltage or by narrow channel effects. However, it progressively deteriorates when the channel is shortened. Except in weak inversion, it is also degraded by structural nonhomogeneities along the channel. This property can be exploited by means of the concept of pseudo-resistors to implement transistor-only linear circuits in the current domain.

Spin correlations at hopping are known to be responsible for large magnetoresistance at trap-assisted tunneling between normal metal and ferromagnetic electrodes. The reason is the spin-selective escape rate, which results in a non-zero average spin at a trap. Since the spin on a trap is a vector quantity, it produces unusual correlations in multi-terminal devices. We analyze a three-terminal device with ferromagnetic electrodes and demonstrate that the spin correlations result in current-voltage dependences characteristic to a single-electron transistor.

An analytical model for graded channel (GC) fully depleted cylindrical/surrounding gate SOI MOSFET has been developed to study the short channel effects (SCEs). The model assumes a steep transition for silicon film doping at the boundary of high/low doped regions and takes into account the effect of the doping and length of the two regions. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain an expression for threshold voltage (Vth)

This monograph presents a detailed derivation and results of experimental verification of the new time- and frequency-domain quasi-2D NQS four-terminal small-signal MOSFET models which take into account the DIBL effect. The monograph is arranged as follows.
The purpose of Chapter 2 is to give a physical background to the new time- and frequency-domain small-signal models. Theoretical discussion and results of numerical analysis in 2D space are given in order to introduce the following three phenomena: gradual channel detachment effect (GCDE), channel thickness modulation effect (CTME), and channel-lengthening
effect (CLE). Based on these phenomena, a quasi-2D dc channel representation and a quasi-2D dc representation of the MOSFET are defined.
In Chapter 3, a novel quasi-2D NQS four-terminal time-domain small-signal MOSFET model is presented. A set of partial differential equations for the new physics-based small-signal model is derived. The set consists of a quasi-2D small-signal continuity equation, a quasi-2D small-signal Poisson’s equation, and a quasi-2D small-signal transport equation. All the equations give a mathematical description of the behavior of the carriers
in the channel and charges in the gate and the body. A set of supplementary equations for coupling and non-capacitive displacement currents in the MOSFET under dynamic operation is also derived. Based on the quasi-2D dc MOSFET representation, a useful formula for the
gate-to-body capacitance Cgb is derived, and some rules dealing with channel-to-gate and channel-to-body coupling currents are established. Reciprocal capacitances occurring in this model are defined. The model we propose in this chapter provides the background to a novel frequency-domain small-signal MOSFET model.
In Chapter 4, a novel DIBL-included quasi-2D NQS four-terminal frequency-domain small-signal MOSFET model is proposed. The model takes into account: the velocity saturation effect of carriers in the channel; the dependence of the mobility on electric field; the electrical coupling between the perturbed charge in the channel and the gate and the body; local variations in the channel thickness; and the DIBL effect. Unlike other models, this one is composed only of reciprocal capacitances. A closed set of partial differential equations defining the model in the time domain is formulated and solved in the frequency domain. The solution indicates that two types of waves can propagate from the source to the drain, viz., a longitudinal wave of a disturbance in the carrier density and a transverse wave of a disturbance in the channel thickness. A closed set of equations for frequency-domain non-capacitive terminal currents in the MOSFET under dynamic operation is also derived.
In Chapter 5, the results of experimental verification of the new DIBL-included quasi-2D NQS four-terminal frequency-domain small-signal MOSFET model are presented. For the purpose of the verification, test transistors and dummy structures were designed and fabricated in 0.35-μm technology. The de-embedding procedure is based on the open-short
method, optimized for RF measurement up to 30 GHz of scattering parameters of the transistors in the common source configuration with the use of air coplanar probes (ACPs).

This paper investigates Gate-All-Around Field-Effect Transistors (GAA FETs) as viable solutions for modern low-power and high-performance electronic applications. Through extensive experimental analysis involving fabrication, electrical characterization, and simulation modeling, this study delves into the intrinsic electrical properties and performance metrics of GAA FETs. Key parameters such as threshold voltage, leakage current, sub-threshold swing, and transconductance are rigorously examined to assess the transistor's operational efficiency for low-power applications. Additionally, advanced simulation models are developed and validated to accurately predict GAA FET behavior, facilitating future design enhancements for high-performance computing. The findings underscore the advantageous features of GAA FETs, positioning them as promising candidates for fulfilling the requirements of both low-power consumption and high-performance computing. This research establishes a foundation for leveraging GAA FET technology in the development of innovative electronic devices, thereby opening avenues for diverse applications across various technological domains.

As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless accumulation-mode MOSFET (Cyl-JLAM MOSFET) to analyse its behaviour in the subthreshold region. The two-dimensional Poisson equation is solved to develop the analytical model by approximating the potential profile along the channel to be parabolic. We have formulated the expression for potential at the centre and electric field along the channel from the developed model. The key performance factors of SCEs including threshold voltage (V TH) roll-off, drain-induced barrier lowering and subthreshold slope are explored with respect to the geometry of the device parameters, i.e. body thickness of the cylindrical silicon pillar, length of the channel and thickness of the oxide layer. The results of our model are in good agreement with numerical simulations. The TCAD ATLAS 3D device simulator accounts for all the physical models required during the simulation. In this paper, the simple and distinctly formulated analytical model supports the application of the Cyl-JLAM MOSFET in integrated circuit design and optimization.

Transistor models are of utmost importance for device behaviour prediction and circuit design. Physical modelling has the advantage of the parameters being correlated based on device physics. This allows to gain insight on the device during the analysis and extraction of parameters phase. However, the extraction methods may not consider possible non-idealities of the device, which can cause modelling issues when working with novel thin film transistors (TFTs). A simple physical DC and AC model was applied to a novel zinc tin oxide TFT annealed at low temperatures (200 oC). The characteristic curves of four devices with different dimensions were measured and analysed, and the model parameters were extracted. The characterization and optimization of the models were implemented through the analysis of the fitting with the measured data. Two DC models were developed, the main difference being the contact resistance extraction using the classic transmission-line method or a procedure bas...

This paper investigates Gate-All-Around Field-Effect Transistors (GAA FETs) as viable solutions for modern low-power and high-performance electronic applications. Through extensive experimental analysis involving fabrication, electrical characterization, and simulation modeling, this study delves into the intrinsic electrical properties and performance metrics of GAA FETs. Key parameters such as threshold voltage, leakage current, sub-threshold swing, and transconductance are rigorously examined to assess the transistor's operational efficiency for low-power applications. Additionally, advanced simulation models are developed and validated to accurately predict GAA FET behavior, facilitating future design enhancements for high-performance computing. The findings underscore the advantageous features of GAA FETs, positioning them as promising candidates for fulfilling the requirements of both low-power consumption and high-performance computing. This research establishes a foundation for leveraging GAA FET technology in the development of innovative electronic devices, thereby opening avenues for diverse applications across various technological domains.

Carrier distributions in cross-section of operated SiC power MOSFET were measured using super-higher-order scanning nonlinear dielectric microscopy. Two measurements were carried out; depletion layer distribution analysis for "on"/"off" state and detailed analysis of gate-source voltage (V GS) dependent carrier distribution. In all measurements, tip-sample voltage difference was kept canceled during V GS application in order to avoid unexpected carrier redistribution due to the tip-sample voltage difference. As a result of the former experiment, difference of depletion layer distribution between "off" and "on" state was visualized. An electron channel formation at "on" state was also visualized. Moreover, in the latter experiment, detailed carrier redistribution depending on the V GS was clearly visualized.

Flash-lamp annealing (FLA) has been investigated for crystallization of patterned amorphous silicon (a-Si) in the fabrication of NMOS and PMOS Thin-Film Transistors (TFTs) on display glass. Samples were exposed with a xenon flash irradiance of ∼30 kW/cm 2 and pulse duration of 200 μs, with bolometer measurements showing an integrated energy of ∼6 J/cm 2. Non-selfaligned TFTs fabricated from the resulting polycrystalline silicon demonstrated electron and hole channel mobility values in excess of 300 cm 2 /(Vs) and 100 cm 2 /(Vs), respectively. According to the authors' knowledge, this is the first report of CMOS TFTs demonstrated using the FLA technique.

In this paper, we extract the mobility of ultra-thin, body buried oxide and fully depleted silicon-on-insulator MOSFET, for different front and back-gate configurations. The mobility values are found by using the Capacitance-Gate Voltage and Current-Gate Voltage characteristics. In addition, the maximum electron mobility is calculated for both configurations: SiON/Si (front-gate) and SiO2/Si (back-gate). Based on the mobility peak, it is determined that the electron transport can be improved by a factor of 1.6 for the front gate configuration. This improvement is explained by the back-channel activation. On the other hand, for the back-gate configuration the electron mobility is improved by a factor of 2.5. A second peak is observed in the electron mobility but cannot be appreciated, mainly because of the influence of an additional capacitance.

This paper reports about the extensive electrical characterization, with low distortion and greater reliability, of MOSFET devices at nanometric scales with ultra thin Fully Depleted (FD) type architecture on Silicon-On-Insulator (SOI) technology to reduce the short channel effects. The parameters of nMOS type devices of 10x1 µm 2 gate dimensions with conventional dielectric (SiON) and alternative high-k dielectric (HfO2) are compared. The extracted parameters are: equivalent oxide thickness (EOT), threshold voltage (VT) as a function of the SOI body voltage (VB), transconductance (gm), maximum transconductance (gm,max) and its corresponding relation with mobility. The objective is to find if the classic electrical characterization methodology can be applied to the new ultra thin devices overcoming the challenges and physical difficulties imposed by the SOI technology and to demonstrate if the ultra thin devices behavior is similar to conventional MOSFETs. The semiconductor devices analyzed were provided by the IMEC consortium in Belgium and have been characterized in the new nanoelectronics laboratory at Universidad San Francisco de Quito (USFQ) in Ecuador.

In this paper, we report the effect of SiO 2 capping layer (C/L) on the excimer laser crystallization of an amorphous Si (a-Si) thin film by the-Czochralski (-CZ) process. With a 50-nm-thick C/L on a 50-nm-thick a-Si film, the diameter of a location-controlled grain increased to 6 mm. Single grain (SG) thin-film transistor (TFT) was fabricated with the C/L SiO 2 as a part of the gate oxide. SG TFT with 50-nm-thick Si showed improved characteristics compared to that without the C/L SiO 2. A field effect mobility of 340 cm 2 V À1 s À1 and a subthreshold slope of 0.18 V/dec were obtained with the 50-nm-thick Si.

Now-a-days, the development of minimization of device dimension by the improvement of several device structures, among which tunneling field effect transistors (TFETs) play a vital role which reduce various short channel effects (SCEs). In this paper, a GaAs based 2-D analytical model for fully depleted cylindrical gate MOSFET is presented. In this paper, we solve 2D Poisson's equation for GAA MOSFET and derived the expression for surface potential along the channel length with suitable boundary condition. The model is used to study the immunity against SCE offered by the MOSFET structure. Additional the model is used to formulate an analytical expression of the surface potential. Also, the effect of various physical device parameters whose range varies such as for Tube thickness (10nm-1nm), Radius (5-10nm), temperature (100K-700K) on surface potential of the device. The advantages of surface potential are based models to make ease for the upcoming compact MOSFET models. The model has been simulated using MATLAB.

In this paper, the dependence of the capacitance of lateral drain–substrate and source–substrate junctions on the linear size of the oxide trapped charge in MOSFET is simulated. It is shown that, at some range of linear sizes of the trapped charge, the capacitance of lateral junctions linearly depends on the linear size of the trapped charge. The dependence of the difference between drain–substrate and source–substrate capacitances on the linear size of trapped charges is also simulated. The revealed dependence can be used in measurements to estimate the linear size of oxide trapped charges induced by hot carrier injection, which can occur during MOSFET operation at defined conditions.

High-mobility single-grain Si TFTs have been successfully fabricated on a polyimide-coated substrate with solution process of Si. After doctor-blade coating of cyclopentasilane (CPS), a-Si:H was obtained at a temperature below 350°C. With dehydrogenation and crystallization by excimer laser, grains with a maximum diameter of 3 μm were obtained at predetermined positions. Single-grain Si TFTs showed mobilities of 460cm 2 /Vs and 121cm 2 /Vs for electrons and holes, respectively. The devices were transferred onto a PEN foil and operated under a bending diameter as small as 6 mm. The results suggest the proposed technology to be attractive for various innovative applications, not only for driver-integrated flexible displays, but also for ultra-high-frequency RF-ID tag, highly-sensitive bio-medical sensors and eventually for integrated smart-systems on a plastic.

first investigating a standard single-ended ECL OR/NOR gate. The paper deals with testability analysis of differential ECL. The logic behaviour and the drop in performance concerning a very detailed list of possible defects of a high speed ECL-Design was examined. The testcircuit, an AND gate (bandwidth: dc to 3.4 Gb/s), was designed taking into account a low power consumption and a small overhead as it is used for weighted random pattern generation and signature analysis (edge counting) within a Built-In-Self-Test (BIST)-Architecture. It was realized using a 1.2 µm bipolar technology. It will be shown that defects in differential ECL devices may cause redundant or delay faults in respect to operation speed. Hence, the performance and the behaviour of the AND gate under a set of defects were examined in order to get general information about defective differential ECL or E 2 CL circuits. 2. High Speed Bipolar ECL-Circuits A problem of high speed (and consequently of wideband) circuits is that a decreasing gate delay causes an increasing power dissipation.

In this paper, an analytical surface potential and threshold voltage model for surrounding gate metal‐oxide semiconductor field‐effect transistor are proposed considering the quantum mechanical effect (QME). Considering variable Fermi potential along the channel, a simple relation between the eigen energies and the potential energy distribution is also provided for the first time. The variation of surface potential and the threshold voltage due to QMEs are computed analytically without using any numerical iteration technique in the model. QME on drain‐induced barrier lowering and threshold voltage roll‐off are also studied to provide a more accurate model. The proposed models are compared with existing surface potential and threshold voltage models and validated by comparing with the simulated results obtained from the 2D device simulator ATLAS of Integrated Systems Engineering Technology Computer Aided Design (ISE TCAD). Very good agreement of our model with TCAD is obtained for a ...

A quasi-Fermi potential based analytical subthreshold drain current model for linear profile based DHDMG MOS transistor, incorporating the fringing fields at the two ends of the device, without the use of any fitting parameter as is the case with drift-diffusion approach is proposed. The model uses an average doping concentration expression. A pseudo-2D analysis applying Gauss' law along the surface is used to model the subthreshold surface potential. The same model is used to find the threshold voltage and drain current for Gaussian profile based DHDMG. A detailed comparison of the proposed Gaussian model with the previously proposed linear model is also presented. The proposed model is also compared with Double gate MOSFET and better performance in terms of DIBL effect reduction is observed. The results obtained are compared with a 2D device simulator DESSIS. Very good agreement of the results from DESSIS with those from the proposed model validates the model for suppressing the short channel effects.

Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent-parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

This article presents the results of an experimental verifica tion of the New Non Quasi Static (NQS) Small Signal MOSFET Model proposed in [1,2]. This model is valid in all operating modes, from weak to strong inversion and from nonsaturation to saturation. For the purpose of verification test transistors with de embedding, dummy structures in 0.35 m technology were designed. The procedure of de embedding was based on the open short [3] method, opti mised for RF measurement up to 30 GHz. The results obtained have confirmed aplicability of the model for the small signal MOSFET simulation.

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multi...

This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

In Myanmar, voltage fluctuation always occurs in electrical supply system. Due to voltage fluctuation, life of electrical equipment consumed electricity is shorted really. To solve this problem, automatic voltage stabilizer is needed for domestic and industries. Both single phase and three phases are available. In this paper intend to known that automatic voltage stabilizer plays efficient role in all type of load i.e. resistive, inductive and capacitive loads. This paper present control circuit for automatic voltage stabilizer provides voltage comparator, relays and servo-controlled motor that compare instantaneous input and output voltage. Automatic voltage stabilizer consists of two unit; measuring unit and regulating unit. In this stabilizer, toroidal type variable autotransformer is used for regulating unit and electronic control circuit is used for sensing unit. Electromechanical or servo control system is used for measuring unit to sense the supply voltage. This electronic control circuit will operate within the fluctuation range from 120V to 250V.The rating of this automatic voltage stabilizer is 7kVA (single phase) and its frequency range is 50Hz. The output sensitivity is ±1%. If input voltage is lower than 120V or higher than 250V, the system will be automatic shutdown.

This paper presents an efficient method to improve the heating effects in Nanoscale SOI MOSFET with the Vertical Gaussian Doping Profile in Drain and Source regions (D-S-G-SOI). Three different structures are investigated: uniform drain (C-SOI), Gaussian drain doping profile (D-G-SOI) SOI MOSFET, and drain-source region with Gaussian doping profile (D-S-G-SOI) and results are compared. Gaussian doping function parameters like standard variation (σ) are used in our study. The proposed structure has been compared with other structures in terms of the lattice temperature, sub-threshold slope, electric potential, electric field, DIBL, leakage current, and floating body (Kink effect). Our results show the excellent electrical and thermal performance of the proposed structure taken account of as a proper substitution for the conventional device.

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.

This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi-finger layouts. The doughnut style involves the polygonal and the 4-sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut and the narrow-OD with multi-fingers versus multi-OD with multi-fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cutoff frequency (fT) and the maximum frequency (fMAX), whereas the noise parameters involved are noise resistance (RN) and the minimum noise figure (NFmin). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (Gm); gate resistance (Rg); effective mobility (μeff); and parasitic capacitances (cgg and cgd). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4-sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in fT and fMAX, owing partly to the improvement in Gm, μeff, cgg, cgd and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in fT due to a lower Gm. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for fT, fMAX, Gm and μeff but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of cgg as the transistor becomes narrower, whereas a multi-OD multi-finger may have high Rg and therefore may lead to the increase of fT and fMAX as the transistor becomes narrower. Besides, the doughnut layout style has a higher Gm and fT, leading to larger μeff from the elimination of shallow trench isolation (STI) stress.

Vending machine that dispense items like as snacks, coffee, beverages, lottery ticket, consumer products automatically when a customer insert a coin or token are increasing rapidly in metropolitan's cities due to contemporary and fast life style requiring excellent quality products. This paper give the details account of the designing and implementation of a multi select state vending machine using State Machine with which users can select the product and insert the desired token for respective products to dispense the Integrated Circuit (IC) or it will return the inserted token if wrong token is inserted for each Integrated Circuit (IC). We choose FPGA for this vending machine since FPGA based vending give quicker response and absorbed less power and reprogrammed anytime as compared to CMOS vending machine. The intended design is implemented in VHDL and simulated using Xilinx VIVADO 2019.1 and it's implemented on FPGA basy-3 Artix 7 series FPGA (xc7a200tfbg676) development board. Synthesis results and FPGA experimental results are shown in this paper.

In this paper we propose a new dual gate SOI-MOSFET in order to reduce short-channel effects (SCEs). In the proposed structure, the bias of the second gate which is near the drain is dependent on the drain voltage. To investigate transistor characteristics, a two-dimensional (2-D) analytical model for the surface potential variation along the channel is developed. A comparison between our structure and the single-gate (SG) SOI MOSFET demonstrates that short channel effects like, hot carriers effect and the drain induced barrier lowering (DIBL) are reduced considerably in the proposed structure.

An improved surface-potential-based metaloxide-semiconductor field-effect transistor (MOSFET) model is presented. The improvement consists in introducing a new generalized logistic functional form for the smoothing factor that allows for a continuous transition of the surface potential from the depletion to strong inversion region. This functional form takes into account specific changes in the technological characteristics of MOSFET devices. The model combines the advantages of both regional and singlepiece models and satisfies all requirements for compact models, i.e., continuity, accuracy, scalability, and simulation performance. Comparison with numerical data shows that the model provides an accurate description of the surface potential for a wide range of substrate doping and oxide thickness.

In the present paper a temperature dependent analytical model for poly-crystalline silicon TFT incorporating the short channel effects and inverse narrow width effects is developed. The temperature dependent modeling parameters and the effect of fringing capacitances are considered to evaluate the drain current, transconductance and cutoff frequency etc. The effect of change in mobility with gate voltage has also been incorporated and the results so obtained show excellent match with the experimental results thus proving the validity of our model.

A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poisson's equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.

Now-a-days, the development of minimization of device dimension by the improvement of several device structures, among which tunneling field effect transistors (TFETs) play a vital role which reduce various short channel effects (SCEs). In this paper, a GaAs based 2-D analytical model for fully depleted cylindrical gate MOSFET is presented. In this paper, we solve 2D Poisson's equation for GAA MOSFET and derived the expression for surface potential along the channel length with suitable boundary condition. The model is used to study the immunity against SCE offered by the MOSFET structure. Additional the model is used to formulate an analytical expression of the surface potential. Also, the effect of various physical device parameters whose range varies such as for Tube thickness (10nm-1nm), Radius (5-10nm), temperature (100K-700K) on surface potential of the device. The advantages of surface potential are based models to make ease for the upcoming compact MOSFET models. The model has been simulated using MATLAB.