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Figure 3. Best-case linear & log scale CMOS transfer characteristics from FLAPS TFTs with Linask = 32 pm and W = 100 pm.

Figure 3 Best-case linear & log scale CMOS transfer characteristics from FLAPS TFTs with Linask = 32 pm and W = 100 pm.

Related Figures (3)

Figure 1. Optical microscope image of FLAPS during TFT fabrication, pre- senting a boron-implanted mesa following FLA exposure and oxide etch fot the source/drain contacts. The outer set of dashed lines represent a demarcatior between the implanted and channel regions, with Lingsk = 32 \.m indicating the mask-defined channel length. The inner set of dashed lines separated by 26 «.m identifies an apparent boundary that may relate to lateral diffusion. The channel region exhibits circular voids (white borders) as well as other visual artifacts.
Figure 1. Optical microscope image of FLAPS during TFT fabrication, pre- senting a boron-implanted mesa following FLA exposure and oxide etch fot the source/drain contacts. The outer set of dashed lines represent a demarcatior between the implanted and channel regions, with Lingsk = 32 \.m indicating the mask-defined channel length. The inner set of dashed lines separated by 26 «.m identifies an apparent boundary that may relate to lateral diffusion. The channel region exhibits circular voids (white borders) as well as other visual artifacts.
Figure 2. NMOS (left) and PMOS (right) transfer characteristics from devices with Linask = 32 4m and W = 100 jm. Note differences in x-axis scale. Each plo has an overlay of over 30 devices measured within a single-shot FLA exposed region. The on-state and off-state operational parameters for the best- case transfer characteristics shown in Fig. 3 were extracted once Ley was established, with results listed in Table I. The width (W) of the TFTs was taken as the designed value of 100 im. The gate oxide capacitance was calculated using the verified deposition thickness of 100 nm. The channel mobility values were calculated from the
Figure 2. NMOS (left) and PMOS (right) transfer characteristics from devices with Linask = 32 4m and W = 100 jm. Note differences in x-axis scale. Each plo has an overlay of over 30 devices measured within a single-shot FLA exposed region. The on-state and off-state operational parameters for the best- case transfer characteristics shown in Fig. 3 were extracted once Ley was established, with results listed in Table I. The width (W) of the TFTs was taken as the designed value of 100 im. The gate oxide capacitance was calculated using the verified deposition thickness of 100 nm. The channel mobility values were calculated from the
Figure 4. SEM image and EBSD mapping (above) of a FLAPS TFT channel region taken from a deprocessed PMOS device verified operational. The boxed region on the SEM image was used for EBSD analysis. Each color (gray tone) represents a different crystal orientation.
Figure 4. SEM image and EBSD mapping (above) of a FLAPS TFT channel region taken from a deprocessed PMOS device verified operational. The boxed region on the SEM image was used for EBSD analysis. Each color (gray tone) represents a different crystal orientation.
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Materials ScienceChemistryThin Film TransistorAmorphous Silicon
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