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Figure 3. (a) A figure depicting a cross-fin cut showing high-k metal gate extension beyond the bottom sheet due to poor process control. As the metal depth below the bottom device increases, the performance penalty due to increased C,¢ fective also increases. (b) A figure showing improved process control due to full bottom dielectric isolation (FBDI) in the source/drain region. Figure 3. (a) A figure depicting a cross-fin cut showing high-k metal gate extension beyond the

Figure 3 (a) A figure depicting a cross-fin cut showing high-k metal gate extension beyond the bottom sheet due to poor process control. As the metal depth below the bottom device increases, the performance penalty due to increased C,¢ fective also increases. (b) A figure showing improved process control due to full bottom dielectric isolation (FBDI) in the source/drain region. Figure 3. (a) A figure depicting a cross-fin cut showing high-k metal gate extension beyond the

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Figure 1. This figure shows a FinFET and a GAA nanosheet FET side-by-side. (a) A FinFET with shallow trench isolation (STI), source/drain (S/D) epitaxy, and a high-k metal trigate is depicted schematically. (b) A GAA nanosheet FET with STI, S/D epitaxy, bottom dielectric isolation (BDI), and high-k all-around metal is pictured. Some features, such as BDI and isolation between gate and S/D, are unique to the GAA nanosheet FETs. resolution, whereas this channel thickness (also referred to as Ts;, thickness of silicon) is defined through epitaxially grown layers of Si on top of epitaxially grown layers of low concentration germanium SiGe, providing superior channel uniformity across wafer, and eliminating process complications.
Figure 1. This figure shows a FinFET and a GAA nanosheet FET side-by-side. (a) A FinFET with shallow trench isolation (STI), source/drain (S/D) epitaxy, and a high-k metal trigate is depicted schematically. (b) A GAA nanosheet FET with STI, S/D epitaxy, bottom dielectric isolation (BDI), and high-k all-around metal is pictured. Some features, such as BDI and isolation between gate and S/D, are unique to the GAA nanosheet FETs. resolution, whereas this channel thickness (also referred to as Ts;, thickness of silicon) is defined through epitaxially grown layers of Si on top of epitaxially grown layers of low concentration germanium SiGe, providing superior channel uniformity across wafer, and eliminating process complications.
Figure 2. This figure shows a schematic for a gate-all-around nanosheet FET, with its key features highlighted. (a) shows a cut across the source-drain region where the key features highlighted are the bottom dielectric isolation (BDI), the thickness of the silicon channels (Ts;), the distance between the silicon channels (T5,,s), and the gate length (Lg). The inner spacer, and the n-type epi are also highlighted here. (b) shows a cut across the gate region where the key features highlighted are shallow trench isolation (STI), n-type work function metal (WFM), p-type WFM, the high-k metal gate (HKMG), and the sheet width (Weyect).
Figure 2. This figure shows a schematic for a gate-all-around nanosheet FET, with its key features highlighted. (a) shows a cut across the source-drain region where the key features highlighted are the bottom dielectric isolation (BDI), the thickness of the silicon channels (Ts;), the distance between the silicon channels (T5,,s), and the gate length (Lg). The inner spacer, and the n-type epi are also highlighted here. (b) shows a cut across the gate region where the key features highlighted are shallow trench isolation (STI), n-type work function metal (WFM), p-type WFM, the high-k metal gate (HKMG), and the sheet width (Weyect).
Figure 4. This figure captures key performance metrics for GAA FETs using PTS scheme and full BDI. (a) Iso ff extracted from Ly =12 nm devices on PTS and BDI splits. (b) DIBL extracted from Ly =12 nm devices on BDI and PTS splits. (c) Power vs. performance correlation chart of wide sheet devices for both with and without BDI layer [24]. As seen in Figure 4, full bottom dielectric isolation reduces the off-state leakage current and the DIBL, thereby improving performance and decreasing power. An 18% decrease in power is observed with a 4% improvement in performance between split with and without BDI. The devices with BDI perform better, and they also show better immunity to process variations with respect to sub-channel leakage control. So, full bottom dielectric isolation may be considered as a critical element for enabling a well-performing GAA nanosheet FET.
Figure 4. This figure captures key performance metrics for GAA FETs using PTS scheme and full BDI. (a) Iso ff extracted from Ly =12 nm devices on PTS and BDI splits. (b) DIBL extracted from Ly =12 nm devices on BDI and PTS splits. (c) Power vs. performance correlation chart of wide sheet devices for both with and without BDI layer [24]. As seen in Figure 4, full bottom dielectric isolation reduces the off-state leakage current and the DIBL, thereby improving performance and decreasing power. An 18% decrease in power is observed with a 4% improvement in performance between split with and without BDI. The devices with BDI perform better, and they also show better immunity to process variations with respect to sub-channel leakage control. So, full bottom dielectric isolation may be considered as a critical element for enabling a well-performing GAA nanosheet FET.
Figure 5. A TEM cross-section of GAA nanosheet FETs. The Ts; is uniform in thickness along the Weneet direction [23].
Figure 5. A TEM cross-section of GAA nanosheet FETs. The Ts; is uniform in thickness along the Weneet direction [23].
As seen in Figure 6a, the degradation of 1, is attributed to increased phonon scattering with thinner Ts;. At high fields, as in the case of Ning at 1015, the mobility is dominated by surface roughness, whereas the peak mobility is primarily impacted by phonon scatter ing. So, the impact of mobility degradation is more profound for the peak mobility case However, this degradation of mobility is offset by sheet width W.y..; as seen in Figure 6b which is primarily influenced by the contribution of <100> vs. <110> planes. Wider sheets have more contribution from the <110> plane, resulting in improved mobility, suggesting that both phonon scattering and sheet geometry effects impact hole mobility. Moreover this dependence on Wy. provides an additional knob for power and performance co: optimization in GAA nanosheet FETs. Figure 6. (a) This plot shows the extracted peak hole mobility and hole mobility for Ninp@10!3 /cm?2 as a function of silicon channel thickness. Degradation in hole mobility is evident for thin sheet values; (b) calculated <100> plane contribution to total W, ff asa function of Ts; (a pure geometrical percentage of the whole nanosheet perimeter) [23].
As seen in Figure 6a, the degradation of 1, is attributed to increased phonon scattering with thinner Ts;. At high fields, as in the case of Ning at 1015, the mobility is dominated by surface roughness, whereas the peak mobility is primarily impacted by phonon scatter ing. So, the impact of mobility degradation is more profound for the peak mobility case However, this degradation of mobility is offset by sheet width W.y..; as seen in Figure 6b which is primarily influenced by the contribution of <100> vs. <110> planes. Wider sheets have more contribution from the <110> plane, resulting in improved mobility, suggesting that both phonon scattering and sheet geometry effects impact hole mobility. Moreover this dependence on Wy. provides an additional knob for power and performance co: optimization in GAA nanosheet FETs. Figure 6. (a) This plot shows the extracted peak hole mobility and hole mobility for Ninp@10!3 /cm?2 as a function of silicon channel thickness. Degradation in hole mobility is evident for thin sheet values; (b) calculated <100> plane contribution to total W, ff asa function of Ts; (a pure geometrical percentage of the whole nanosheet perimeter) [23].
Figure 7. This figure shows a close up view of the S/D cross-section. The width of the high-k metal gate here is the gate length Lg, and the vertical thickness of this metal gate is determined by Tsys. Additionally, the inner spacers and bottom dielectric isolation are highlighted. Figure 7. This figure shows a close up view of the S/D cross-section. The width of the high-k metal The ability to co-integrate multiple threshold voltages (Vr) is a key requirement for a technology to become an industry standard. Given the unique architecture of GAA FETs, the space for depositing the work function metals is limited as depicted in Figure 7. The replacement metal gate process only leaves the space between the Si channels and inner spacers open—to be filled with the work function metals as per technology requirements. This space, also known as Tsys5 (refer Figure 2), can be controlled by controlling the thickness of SiGe layer grown during the nanosheet stack development module, but is nevertheless highly constrained, and must be engineered carefully to meet the industry standards for device offerings.
Figure 7. This figure shows a close up view of the S/D cross-section. The width of the high-k metal gate here is the gate length Lg, and the vertical thickness of this metal gate is determined by Tsys. Additionally, the inner spacers and bottom dielectric isolation are highlighted. Figure 7. This figure shows a close up view of the S/D cross-section. The width of the high-k metal The ability to co-integrate multiple threshold voltages (Vr) is a key requirement for a technology to become an industry standard. Given the unique architecture of GAA FETs, the space for depositing the work function metals is limited as depicted in Figure 7. The replacement metal gate process only leaves the space between the Si channels and inner spacers open—to be filled with the work function metals as per technology requirements. This space, also known as Tsys5 (refer Figure 2), can be controlled by controlling the thickness of SiGe layer grown during the nanosheet stack development module, but is nevertheless highly constrained, and must be engineered carefully to meet the industry standards for device offerings.
Figure 8. An example of Vr modulation as presented in [21] is shown here. (a) The gate region post SiGe channel release; (b) WFM1 deposition; (c) sacrificial material deposition; (d) selective patterning and etch of the deposited WFM; and (e) removal of patterning stack resulting in a structure with WEM1 along one set of sheets.
Figure 8. An example of Vr modulation as presented in [21] is shown here. (a) The gate region post SiGe channel release; (b) WFM1 deposition; (c) sacrificial material deposition; (d) selective patterning and etch of the deposited WFM; and (e) removal of patterning stack resulting in a structure with WEM1 along one set of sheets.
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