MOSFET compact modeling

An analyticalmodelofCGAAMOSFETincorporatingmaterialengineering,channelengineeringandstack
engineering hasbeenproposedandverified usingATLAS3Ddevicesimulator.Acomparativestudyof
short channeleffectsforvariousdevicestructureshasalsobeencarriedoutincorporatingtheeffectof
drain inducedbarrierlowering(DIBL),thresholdvoltageloweringanddegradationofsubthresholdslope.
The effectivenessofapplyingthethreeregiondopingprofile conceptinthechannelsuchashigh-
medium-low andlow-high-lowanditscomparisonwithGaussiandopingprofile tothecylindricalGAA
MOSFET hasbeenexaminedindetail.ReducedSCEshavebeenevaluatedincombineddesignsi.e.
TM–GC–GS, GCGSandDM–GC–GS. Outofseveraldesignengineering,GC–GS CGAAgivesnearlyideal
subthreshold slopewhereasTM–GC–GS CGAAprovidesoverallsuperiorperformancetoreduceSCEsin
deep nano-meter.Theresultssoobtainedareingoodagreementwiththesimulateddatawhichvalidate
the model

The current SOI MOSFET technology supports the scaling down to nanometer regime but it is unable to keep the performance level high as it suffers from the restrictions like effective interface coupling, channel orientation, channel mobility, off-state leakage, switching delay and latch up. The additional parameters such as injection velocity, short channel length effects, narrow channel effects, body effects, hot carrier effect, depletion width effect, substrate doping effect and Band-to-Band Tunneling (BTBT) also results in decrease of inversion charge, increase in leakage current and decrease in the drive current. In order to minimize these effects, double gate came into existence, which relies on the exploration of novel higher mobility channel materials such as SiGe, which might perform even better than Si. This paper reviews the double-gate N-MOSFET using SiGe as channel material.

A simple new architecture of phase frequency detector with low power and low phase noise is presented in this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm technology. Floating gate based methodology reduced the power of phase frequency detector about 51%. Introduction of floating gate based phased frequency detector also reduces the number of transistor as compared with conventional phase frequency detector.

In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).

This study aimed to investigate the effect of mannan-oligosaccharide (MOS) on the lipogram and selected organ functions in hyperlipidemic rats. Animals were subjected to different treatments for 60 days. Balanced basal diet was supplied to control rats; saturated high fat- and/or MOS-contained diets were supplied to tested rats. Sera were collected on escalating times and total lipids, cholesterol, triacylglycerols, HDL-C, LDL-C, VLDL-C, AST, ALT, urea and creatinine were evaluated. On the last day, rats were sacrificed and the kidneys, liver, heart with aorta were picked out for histopathology. The results of MOS-treated group revealed significant decrease in total lipids, cholesterol, LDL-C, VLDL-C, AST, ALT, urea and creatinine with significant increase in HDL-C. Histopathological findings in the tested organs have been ameliorated with MOS, comparing with those in hyperlipidemic rats. The obtained data may give MOS the potential of antihyperlipidemic activity for prophylaxis and treatment of hyperlipidemia and related diseases.

Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.

Enhancement of switching in nanoelectronics, Carbon Nano Tube (CNT) could be utilized in nanoscaled Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In this review, we present an in depth discussion of performances Carbon Nanotube Field Effect Transistor (CNTFET) and its significance in nanoelectronic circuitry in comparison with Metal Oxide Semiconductor Field Effect Transistor (MOSFET). At first, we have discussed the structural unit of Carbon Nanotube and characteristic electrical behaviors beteween CNTFET and MOSFET. Short channel effect and effects of scattering and electric field on mobility of CNTFET and MOSFET have also been discussed. Besides, the nature of ballistic transport and profound impact of gate capacitance along with dielectric constant on transconductance have also have been overviewed. Electron ballistic transport would be the key in short channel regime for high speed switching devices. Finally, a comparative study on the characteristics of contact resistance over switching capacity between CNTFET and MOSFET has been addressed.

Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher current range, very low power dissipation and higher matching accuracy. It achieves current range of up to 1500 µA, high output impedance of 1.125 T, bandwidth of 4.1 MHz and dissipates power as low as 10.56 µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS process technology with +1.0 Volt single power supply.

In this work, we study analytical model such threshold voltage (V TH) and Subthreshold swing (SS) for a new Surrounding Gate MOSFET. This new SG-MOSFET is composed of Dual-metal Gate (DMG) M 1 and M 2 with different work function, Graded Channel (GC) whose the doping is higher near the source side than the drain side and Dual Oxide Thickness (DOT). Analytical model for V TH and SS are developed by solving 2D Poisson equation using parabolic approximation method. Results for new device are compared to those obtained by numerical simulation and have been found to be in good agreement. Comparative study between (DMG-GC-DOT) SG MOSFET and with different device engineering shows that the new structure provides improved electron transport and reduced short channel effects (SCE).

The performance of modern MOSFETs is limited by the presence of parasitic series resistances and mobility degradation. This article reviews and assesses 18 of the extraction methods currently used to determine the values of parasitic series resistances and mobility degradation from the measured drain current. The methods are separated in 3 groups: seven different methods that use the transfer characteristics of several devices having different mask channel lengths; five methods based on a single device with different drain and gate bias; six methods which account for the asymmetry between drain and source resistance.

Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the growing semiconductor industry. The need to procure low power dissipation, high operating speed and small size requires the scaling down of these devices. This fully serves the Moore's Law. But scaling down comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use of SED based devices prove to be a better solution to device downsizing has been presented. As such the study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study of the properties of several Quantum dot materials and how to choose the best material depending on the observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of electrons with the help of a quantum wire has been presented.

Nowadays, Vending Machines are well known among Japan, Malaysia and Singapore. The quantity of machines in these countries is on the top worldwide. This is due to the modern lifestyles which require fast food processing with high quality. This paper describes the designing of multi select machine using Finite State Machine Model with Auto-Billing Features. Finite State Machine (FSM) modelling is the most crucial part in developing proposed model as this reduces the hardware. In this paper the process of four state (user Selection, Waiting for money insertion, product delivery and servicing) has been modelled using MEALY Machine Model. The proposed model is tested using Spartan 3 development board and its performance is compared with CMOS based machine.

—A charge-based compact model of the long-channel cylindrical surrounding-floating gate (S-FG) MOSFETs for memory cell application is presented. The compact model is based on an accurate extraction of floating gate potential using charge balance model and solving the mobile charge density at the source and drain ends using the unified charge control model (UCCM). The drain-current relation is obtained from Pao-Sah's dual integral, which is expressed as a function of inversion charge at the source and drain end. The compact model for the floating gate potential and its transfer characteristics have been extensively verified with numerical simulations at various bias potentials and floating gate charges in all operating regions.

An explicit solution for long-channel surrounding-gate (SRG) MOSFETs is presented from intrinsic to heavily doped body including the effects of interface traps and quantum effects. The solution is based on the core SRGMOSFETs model of Unified Charge Control Model (UCCM) for heavily doped condition. The UCCM model of highly doped SRGMOSFETs is derived to obtain the exact equivalent expression as in undoped case. Taking the advantage of the undoped explicit charge-based expression, the asymptotic limits for below threshold and above threshold have been redefined to include the effect of trap states for heavily doped case. After solving the asymptotic limits, an explicit mobile charge expression is obtained which include the trap state effects. The explicit mobile charge model shows very good agreement with respect to numerical simulation over practical terminal voltages, doping concentration, geometry effects, and trap state effects due to the fixed oxide charges and interface traps. Then, the drain current is obtained using the Pao–Sah's dual integral, which is expressed as a function of inversion charge densities at the source/drain ends. The drain current agreed well with implicit solution and numerical simulation for all regions of operation without employing any empirical parameters. In addition, the quantum effects are included based on quantum corrected model. The threshold voltage shift due to quantum confinement is incorporated to the classical model and the effective gate capacitance is recalculated due to series connected quantum capacitance. Comparison with previous explicit model has been conducted to verify the competency of the proposed model with doping concentration of 1 × 10 19 cm −3 as the proposed model has better advantages in terms of its simplicity and accuracy at higher doping concentration.

— Extrinsic parasitic series resistance and mobility degradation are two important parameters limiting the performance of multifinger microwave MOSFETs. In this paper, we present a method to extract these parameters from measured drain-voltage versus gate-voltage characteristics at given constant values of drain current. Measured data of multifinger microwave MOSFETs are used to test and verify the developed method. The method requires only simple dc measurements on a single test device.

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using l-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350°C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-inpackage, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 lm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f T , in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.

—Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent-parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented.

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using l-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350°C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-inpackage, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 lm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f T , in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.

We propose here a simple approximate, yet accurate, formula to easily calculate the maximum magnitude of the electric potential at the channel width's midpoint of symmetric Double Gate (DG) MOSFETs with any arbitrary body doping concentration. According to it this maximum magnitude depends only on the body's thickness and doping concentration, apart from its usual dependence on quasi-Fermi level splitting. The new formula allows to easily determine the critical body thickness value above which any arbitrarily doped symmetric DG MOSFET can be satisfactorily modeled using a conventional bulk MOSFET model. This critical value depends only on body doping concentration, The proposed approximate formula also constitutes a useful means to quickly calculate initial values in iterative numerical calculations of doped symmetric DG MOSFET models.

Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.

Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the growing semiconductor industry. The need to procure low power dissipation, high operating speed and small size requires the scaling down of these devices. This fully serves the Moore's Law. But scaling down comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use of SED based devices prove to be a better solution to device downsizing has been presented. As such the study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study of the properties of several Quantum dot materials and how to choose the best material depending on the observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron transistor is reviewed. Also a theoretical explanation to...

Nowadays, Vending Machines are well known among Japan, Malaysia and Singapore. The quantity of machines in these countries is on the top worldwide. This is due to the modern lifestyles which require fast food processing with high quality. This paper describes the designing of multi select machine using Finite State Machine Model with Auto-Billing Features. Finite State Machine (FSM) modelling is the most crucial part in developing proposed model as this reduces the hardware. In this paper the process of four state (user Selection, Waiting for money insertion, product delivery and servicing) has been modelled using MEALY Machine Model. The proposed model is tested using Spartan 3 development board and its performance is compared with CMOS based machine.

Keywords: Double Gate MOSFET Symmetric DG MOSFET Doped-body DG MOSFET Undoped-body DG MOSFET a b s t r a c t We propose here a simple approximate, yet accurate, formula to easily calculate the maximum magnitude of the electric potential at the channel width's midpoint of symmetric Double Gate (DG) MOSFETs with any arbitrary body doping concentration. According to it this maximum magnitude depends only on the body's thickness and doping concentration, apart from its usual dependence on quasi-Fermi level splitting. The new formula allows to easily determine the critical body thickness value above which any arbitrarily doped symmetric DG MOSFET can be satisfactorily modeled using a conventional bulk MOSFET model. This critical value depends only on body doping concentration, The proposed approximate formula also constitutes a useful means to quickly calculate initial values in iterative numerical calculations of doped symmetric DG MOSFET models.