Introductory Chapter: Integrated Circuit Chip

Proceedings of the IEEE, 1998

IFIP Advances in Information and Communication Technology, 2011

By 2020 it is very likely that nano-CMOS will reach the end of the scaling roadmap. Such end will not mean the demise of silicon technology at all. While there are uncertainties as to what will be the show-stoppers, there is a large number of transitional and compatible to CMOS technologies that will be more important than just 2-D scaling. This paper discusses possible limitations bringing the end of scaling and also proposes a likely scenario for hardware technology evolution and related challenges for integrating systems in the next 20 years. The scenario beyond the end of the roadmap is drawn, in which key technologies will be developed to be compatible with nano-scaled CMOS in silicon, and not to replace it entirely. Transitional technologies will rather coexist and be built upon a basic CMOS-like technology platform of silicon-oninsulator. Radically new devices at the 1-10 nm scale will most likely be built on a silicon substrate with the same technical requirements (such as cleanness, lithographic resolution, long-range ordering, etc) of near end-of-roadmap CMOS industry. The end of scaling will not necessarily lead to the onset of a post-silicon era. Advanced materials research has not pointed so far to a nonsilicon scenario well beyond 2020. The computing systems challenges will be dealt with new forms of integration, hierarchically ordered from the micronlevel, to sub-micron level (500nm to 100nm) non-digital, down to nano-scaled transistors on silicon further down to 10 nm. In this hierarchy, at the bottom, it is highly possible that disruptive molecular-level devices (self-assembled in the scale of 2 to 10 nanometers) will eventually be production-worthy for 100 Giga-to Tera-scale devices integration. Structures like graphene-based carbon tubes or planes are the most viable candidates for molecular devices. In this presentation the computer-systems relevant issues of systems power dissipation, noise, hardware design complexity, and resilience to systems failures in the presence of device variances and faults, are addressed as the challenging computing research topics that will guide future research in computing architectures at the tera-scale integration beyond 2020.

2012

The interaction between the design and the technology research communities working in nanoelectronics, and especially in the Beyond CMOS area, is characterised by a diversity of terminologies, modi operandi and the absence of a consensus on main priorities. We present the findings of the EU project NANO-TEC to date, in the quest to bring together these communities for the benefit of a stronger European Research Area. Through this, we present a summary of technology trends and a preliminary benchmarking analysis for a subset of these as an example of the project work. We summarise relevant design issues concerning these technologies and conclude with recommendations to bridge this design-technology gap.

Proceedings of the 38th conference on Design automation - DAC '01, 2001

We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns, thermal monitoring and feedback mechanisms can limit worst-case dissipation and reduce costs. Furthermore, a flexible multi-V dd + multi-V th + re-sizing approach is advocated to leverage the inherent properties of ultrasmall MOSFETs and limit both dynamic and static power. Alternative global signaling strategies such as differential and low-swing drivers are recommended in order to curb the power requirements of crosschip communication. Finally, potential power delivery challenges are addressed with respect to ITRS packaging predictions.

International Journal of Computer …, 2010

IEEE Transactions on Electron Devices, 2008

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

Proceedings of the 2005 IEEE/ACM International …, 2005

Nanoscale technologies provide both challenges and opportunities. We show that the issues and potential solutions facing designers are technology independent and arise mainly from shrinking device sizes and an increase in the number of devices available. We explore how it is possible to use some of the devices that will be available to help ease design complexity as well as overcome process related challenges such as limited layout freedom, increased defect densities, timing constraints, and power dissipation. 0-7803-9254-X/05/$20.00 ©2005 IEEE.

Computing in Science & Engineering, 2003

2012

The VLSI design productivity crisis, that is, the fact that the number of available transistors grows much faster than the ability to design them meaningfully, has become the greatest threat to the growth of semiconductor industry. The cost-performance is rapidly improved as devices are scaled down. This is the reason why the miniaturization has been pursued persistently for these thirty years and will be pursued in the future. As semiconductor geometries continue to shrink and the chips themselves become ever-more complex, the cost of research and development continues to skyrocket. Recently, however, unfavorable effects caused by the scaling have become eminent. First, the power density increases. Secondly, interconnect related quantities increase such as interconnect delay, current density, and noise. Lastly, since the number of devices on a chip increases, the design and test of VLSI’s become more difficult. There are certain key issues that serve as active areas of research and...

We all are living in the digital world where we are going to use many devices which are fabricated using the CMOS technology. Due to the constraint design of the circuits and long routing schemes we are going to make the chip work a lot harder and it results in high power consumption. In order to reduce the power consumption we prefer to use certain techniques like usage of nano-materials instead of conventional Poly-Silicon. In this technique we are interested to modify certain conditions which results in generation of a new kind of technology which results in low power consumed, high speed circuits and devices which make a new way in the world of electronics. To reduce the power consumption of transistor i.e., when compared with ordinary transistor we has to reduce the power consumption as well as the power dissipation [6]. So we propose the application of nano-materials which have high conductivity as well as low ? power dissipation which can be employed in design of Transistors of various technologies ( like 200nm., 100nm., 50nm. etc.,).