Table 1. Calculation of dynamic values Definition 1. We say max{dy/dx;}=1 iff there is at least one combination of values 0 or 1 for nonspecified x’s which produce dy/dx; =1. Otherwise, max {dy /dx;} =0. Table 2. Signal paths and delays of the example Example. An example of SSBDD for the circuit in Fig. 1 is presented in Fig. 2. The nodes of the graph, the corresponding paths in the circuit, and the path delays, calculated by Eq. (1), are depicted in Table 2 (here we assume that all the gates have a unit delay). Fig. 3. Single-stack-based timing simulation for the SSBDD in Fig. 2. Fig. 4. Double-stack-based timing simulation for the SSBDD in Fig. 2. In another stack we find node g with the delay equal to the delay in h,, so we move further to node g and start the traversal of newly activated path from that point. Both stacks are empty again. As the node h, has a transition and the delay is greater than the current moment of time, we put it into one of the stacks. Node k, does not have a transition, so we pass it by and come to the same terminal node (again y =0). Fig. 5. Comparison of simulation times of different algorithms (single-bit transition mode). ood The results for tree-like circuits are illustrated for the case of single transitions in Fig.5 and for the case of multiple transitions in Fig. 6. Simulation time is given in seconds for 30000 random patterns. In our work we measured simulation time on both macro and gate levels. Note that the simulation time grows exponentially with the number of levels at the gate level (Fig. 5). The simulation time at the macro level (our approach) grows much slower (Fig. 5), but also not linearly. In Fig. 5 (right) all the four macro-level algorithms are shown. However, there is no noticeable difference in simulation time between them. Fig. 6. Comparison of simulation times of different algorithms (multiple-bit transition mode). However, Fig. 7 presents an interesting observation that the speed gain of timing simulation is directly proportional to the average size of a macro. The results are shown for the case of ISCAS’85 benchmarks and the double-stack Fig. 7. Simulation speed-up compared to the average size (number of gates) of a macro.
