Can SG-FET Replace FET in Sleep Mode Circuits?

IJMER

In the nanometer range design technologies static power consumption is very important issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards down in respect of size and achieving higher operating speeds. We have also considered these parameters such that we can control the leakage power. As process model design are getting smaller the density of device increases and threshold voltage as well as oxide thickness decrease to maintain the device performance. In this article two novel circuit techniques for reduction leakage current in NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a design model that has significant reduction in power dissipation during inactive (standby) mode of operation compared to classical power gating methods for these circuit techniques. The proposed circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier inverter leakage minimization techniques. All low leakage models of inverters are designed and simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average power, Leakage power, sleep transistor

Low Power SRAMs have become a critical component of many VLSI chips. Power can be reduced by using either dynamic or static power reduction techniques. Power gating is one of the most effective static leakage reduction methods. In power gating sleep transistors are used. They disconnect the cell from power supply during sleep mode leading to 91.6% less static power dissipation but they also helps in reducing the dynamic power by reducing the power supply to the cell. In this paper the effect of sleep transistor in active mode is implemented and resulting SRAM is found to dissipate 32% less power than conventional SRAM.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

Multi-threshold CMOS is a valuable leakage reduction method in circuit standby mode. Reducing leakage current through finegrain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improves circuit noise margins. In this paper, we first indicate the negligible dependence of ST size on the amount of leakage saving which makes the two-phase FGSTI reasonable based on our leakage current and delay models. Then we introduce a novel two-phase FGSTI technique: a) ST placement and b) ST sizing, which are formally modeled as two linear programming (LP) models respectively. Our experimental results show that the two-phase FGSTI technique can achieve 78.91%, 92.55%, 97.97% leakage saving when the circuit slowdown is 0%, 3%, 5% respectively. Comparing to the simultaneous ST placement and sizing method using mix integer linear programming (MLP) [1], our technique leads to on average 2% more leakage current reduction while at least 10X runtime saving since fewer variables and constraints with less approximation are used in the LP models. When the circuit slowdown is large enough to perform conventional fixed slowdown method, our technique can still achieve 75.48% ST area saving. Moreover, we show that when the circuit slowdown is 0%, it should be carefully considered to use FGSTI technique due to a large amount of leakage feedback gates.

2007

We present a new, analytical model for the SGFET that is suitable for hand calculations and time-efficient circuit simulations. Our model expresses the pull-in, pull-out voltages and the stable travel range in terms of the structural parameters and the moving gate position as a function of the gate voltage. Starting from our model, we discuss the influence of the structural parameters on the transistor characteristics and the potential of the SGFET for logic circuits. We also introduce the SGFET SRAM cell to demonstrate the use of our model and to illustrate the interest of the SGFET for ultra-low power applications. SGFET logic gates exhibit a significantly reduced off-state power dissipation and improved functionality as compared to CMOS gates.

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. For the most recent CMOS feature sizes (e.g., 45nm and 65nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. In the nanometer technology regime, power dissipation and process parameter variations have emerged as major design considerations. These problems continue to grow with leakage power becoming a dominant form of power consumption. Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS).This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques at circuit level and process level are used to efficiently minimize leakage current which lead to minimize the power loss and prolong the battery life in idle mode. This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.

This paper concentrates on the various power reduction techniques for clustered sleep transistors and in particular leakage and dynamic power of the gated circuits published recently based on different logic styles. All the advantages and applications of the circuits have discussed with the relevant proofs of results and analytical models. All the circuits are designed and tested using spice simulation models and the screenshots of the different sleep transistor circuits based on Multi-threshold CMOS approach have depicted and its advantages over other methodologies have tested and its spice simulation results has presented with the required analytical model and the final layout of clustered sleep transistor has laid down.

2008

With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper a novel circuit design technique is presented which minimizes sub-threshold leakage current by zeroing drain-source voltage. This results in a reduction of leakage power consumption in sleep mode especially in wide gates. Since leakage power due to sub-threshold current in sub-100nm technologies increases dramatically the proposed circuit design technique is designed to be less dependent on technology scale and temperature. Since there is no additional circuitry needed for power reduction in this circuit design technique, there is no additional circuitry needed for power reduction. Thus, circuit complexity and dies area cost is much less than existing logic families. Moreover, the switching time between sleep mode and active mode is shorter.

2018

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied at device and circuit level to reduce power dissipation of deeply scaled CMOS ICs. However, these approaches have unavoidable drawbacks which affect the performance as well as cost of device. Therefore, there is a strong need to find an emerging technology, which has nearly zero leakage current, but has high drive current, that also can utilize CMOS fabrication and design concepts, and can be integrated with CMOS technology without additional overhead. This paper focuses on the analysis, design, characteristics and applications of MOSFET replacement devic...

2011 12th Latin American Test Workshop (LATW), 2011

CMOS is still the predominating technology for digital designs with no identifiable concurrence in the near future. Driving forces of this leadership are the high miniaturization capability and the reliability of CMOS. The latter, though, is decreasing with an alarming pace against the background of technologies with sizes at the nanoscale. The consequence is a rising demand of solutions to improve lifetime reliability and yield of today's integrated systems. Thereby, a common solution is the redundant implementation of components. However, redundancy collides with another major issue of integrated circuits -power dissipation. The main contribution of this work is an approach that increases the lifetime reliability at only low delay and power penalty. Therefore, the well-known standbyleakage reduction technique "Sleep Transistors" is combined with the idea of redundancy. Additional, we propose an extended flow for reliability verification on transistor level. Simulation results indicate that the new approach can increase the lifetime reliability by more than factor 2 compared to initial designs.