Analyzing the Impact of Sleep Transistor on SRAM

CGC International Journal of Contemporary Technology and Research, 2019

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

2011

SRAM is a type of semiconductor memory which does not need to be periodically refreshed. With scaling down of the technology, the feature sizes have shrink more and more and miniaturization at chip level has occurred. But as a trade off, the demand for power has also increased. SRAM continues to be a critical component across a gamut of microelectronics applications. Leakage is a serious problem particularly for SRAM. To address sub threshold leakage issue sleepy stack approach is used .The sleepy stack SRAM cell design, is a new technique which involves changing the circuit structure as well as using high-V th. The sleepy stack technique achieves greatly reduced leakage power while maintaining precise logic state in sleep mode. This paper compares performance of SRAM using sleepy stack approach with that of conventional design. The impact of temperature and voltage on the performance of sleepy stack design is also analyzed. Berkeley Predictive Technology Model (BPTM), level 49 targeting 0.18μm technology is used. The design is successfully simulated and analyzed using HSPICE tools.

as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool. I. INTRODUCTION As with every generation of technology, the demand of handling the large amount of data in embedded memory has been increasing. To fulfill the requirement handling large data feature size of transistor is continuously reducing. With respect to high transistor density the problem of power consumption is becoming prominent issue to tackle. Static Random Access Memory is the first choice of designing semiconductor embedded memories because of low power dissipation. The low power feature for on chip SRAMs is becoming more important especially for battery operated portable applications .It is however one of the most significant challenges of high density VLSI circuit .The main aim of this paper is to estimate the effect of clustering technique on 6T SRAM cell and to investigate transistor sizing of the 6T SRAM cell for optimum power and delay. In this work , an average power dissipation of 6T SRAM Cell has been compared with SRAM cell using cluster technique.The cluster technique reduces the power dissipation of 6T SRAM cell in read, write , and hold operation .

2015

62 www.ijeas.org  Abstract— Voltage Scaling in CMOS circuits will reduce the threshold voltage, however there is an increase in the sub threshold leakage current and hence static power dissipation. This increase in leakage power dissipation is a concern in VLSI design even for the most recent CMOS feature sizes. To reduce this power dissipation an approach called sleepy keeper is used for CMOS circuits. This approach uses two additional transistors along with the traditional sleep transistors. These additional transistors help to save a logic state during the sleep mode.

The major portion of total power consumption in the integrated device is leakage power dissipation and is expected to grow exponentially in the next decade as per the InternationalTechnology Roadmap For Semiconductor(ITRS).In CMOS circuit, reduction of threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. Some leakage current reduction technique like Sleep Approach, Stack Approach, Lekage Feedback Approach, Zig-Zag Approach, Sleeper Keeper technique, Force Stack Technique and here we use proposed novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques. In this paper we design1 bit SRAM cell by using the LECTOR power reduction techniques. The proposed circuit technique were design in different CMOS/VLSI technology with in MicroWind tool and measure power consumption design approach LECTOR achieves up to 35%-50% leakage reduction over the conventional circuit without affecting the dynamic power.

As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic V DD , negative word line, and bit line floating schemes. All of them are achieved by controlling different terminal voltages of the SRAM cell in standby mode. On the other hand, performance loss occurs simultaneously with leakage saving. To validate the effectiveness of low power techniques, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 45 nm complementary metal-oxide-semiconductor (CMOS) process with leakage current reduction techniques has been simulated. The results indicate that by using the dynamic V DD and source biasing schemes, greater leakage suppressing capability, although with a higher performance loss, can be obtained. Therefore, the SRAM cell optimization scheme must consider the trade-off between power consumption and speed performance.

The major portion of total power consumption in the integrated device is leakage power dissipation and is expected to grow exponentially in the next decade as per the InternationalTechnology Roadmap For Semiconductor(ITRS).In CMOS circuit, reduction of threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. Some leakage current reduction technique like Sleep Approach, Stack Approach, Lekage Feedback Approach, Zig-Zag Approach, Sleeper Keeper technique, Force Stack Technique and here we use proposed novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques. In this paper we design1 bit SRAM cell by using the LECTOR power reduction techniques. The proposed circuit technique were design in different CMOS/VLSI technology with in MicroWind tool and measure power consumption design approach LECTOR achieves up to 35%-50% leakage reduction over the conventional circuit without affecting the dynamic power.

IJMER

In the nanometer range design technologies static power consumption is very important issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards down in respect of size and achieving higher operating speeds. We have also considered these parameters such that we can control the leakage power. As process model design are getting smaller the density of device increases and threshold voltage as well as oxide thickness decrease to maintain the device performance. In this article two novel circuit techniques for reduction leakage current in NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a design model that has significant reduction in power dissipation during inactive (standby) mode of operation compared to classical power gating methods for these circuit techniques. The proposed circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier inverter leakage minimization techniques. All low leakage models of inverters are designed and simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average power, Leakage power, sleep transistor

International Journal of Engineering & Technology, 2018

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T ...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.