Papers by Marius Enachescu
Synchronous Current Switching Technique for Adjusting the CMOS Ring Oscillator Duty Cycle
2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), 2018
The present work proposes a low cost, synchronous current switching technique for adjusting a 60M... more The present work proposes a low cost, synchronous current switching technique for adjusting a 60MHz, medium frequency, oscillator duty cycle. Current switching is necessary due to the use of both charge and discharge delays of the oscillator topology. Added circuitry consists on trimmable current mirrors and synchronizing circuitry. Main goal is not to affect the functionality of the system, nor initial frequency or duty cycle variation. The circuit is designed using sub micrometer technologies, for a supply voltage range between 1.6V and 2V.
OPAMP's finite gain and slew rate impact on a 16-bit ΣΔ ADC performance: A case study
2017 International Semiconductor Conference (CAS), 2017
This paper aims to offer insight into the topic of discrete-time ΣΔ ADCs. More specifically, we i... more This paper aims to offer insight into the topic of discrete-time ΣΔ ADCs. More specifically, we investigate the impact of non-ideal analog subcircuit parameters on the performance of a 16-bit, 1 kHz, differential second order, 1-bit quantizer, sigma-delta modulator in a 180 nm technology. The parameters in question are OPAMPs slew rate and gain which fulfill the role of fully differential, discrete-time integrators. SPICE simulations were used to validate the results obtained in Matlab for each given scenarios.
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 2009
The Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace trad... more The Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace traditional FETs in sleep mode circuits, due to its abrupt switching enabled by electromechanical instability at a certain threshold voltage and its ultra low "off" current (I off ). This paper presents a preliminary assessment of the SG-FET potential if utilized as sleep transistor in real applications, e.g., microprocessors. We first evaluate various SG-FET instances in terms of switching delay, current capability, and leakage. Subsequently, we compare these figures with the ones offered by traditional switch transistors utilized in CMOS technologies. Our simulation results indicate that SG-FET based sleep mode circuits are potentially interesting as they clearly enable substantial leakage reductions due to their extremely low "off" currents (4 orders of magnitude lower than FET) at the expense of a 4x larger active area for the same capability to drive current.
2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013
In this paper, we address the design of wideoperand addition units in the context of the emerging... more In this paper, we address the design of wideoperand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end we first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss the cost and performance of each strategy. Our analysis identifies as a major direct folding drawback the utilization of different structures on each tier. Thus, in order to alleviate this, we propose a novel 3D Stacked Hybrid Prefix/Carry-Select Adder with identical tier structure, which potentially makes the manufacturing of hardware wide-operand adders a reality. Such an N -bit carry select adder can be implemented with K identical tier stacked ICs, where each tier contains two N/K-bit fast prefix adders operating in parallel according to the computation anticipation principle. Their carry-out signals are cascaded through TSVs in order to perform the selection of the sums accordingly, which results in a delay with the asymptotic notation of O(log(N/K) + K). To evaluate the practical implications of direct folding and of the hybrid prefix/carry-select approaches we perform a thorough case study of 65 nm CMOS 3D adder implementations for different operand sizes and number of tiers, and analyze various possible design tradeoffs. Our simulations indicate the hybrid prefix/carry-select approach can achieve speed gains over 3D folding based designs of between 29% and 54%, for 512-bit up to 4096-bit adders, respectively. Even though 3D folding requires less real estate, when considering a more appropriate metric for 3D design, i.e., delay-footprint-cost product, the hybrid prefix/carry-select approach substantially outperforms the folding one and provides delay-footprint-cost reductions between 17.97% and 94.05%.
CAS 2011 Proceedings (2011 International Semiconductor Conference), 2011
In this paper we present a unity-gain follower amplifier based on a gated diode operated in break... more In this paper we present a unity-gain follower amplifier based on a gated diode operated in breakdown regime in common cathode configuration. The amplifier has only one stage and it provides power amplification, high input impedance and a low output one. The maximum frequency that can be applied on the entrance of the amplifier so that the output remains undistorted is dependent on the bias current therefore it can be used also as a programmable low pass filter. The diode is fully characterized in order to set the bias in the linear region where the amplification is very close to one.
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Papers by Marius Enachescu