In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase... more In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. For the most recent CMOS feature sizes (e.g., 45nm and 65nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. In the nanometer technology regime, power dissipation and process parameter variations have emerged as major design considerations. These problems continue to grow with leakage power becoming a dominant form of power consumption. Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS).This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques at circuit level and process level are used to efficiently minimize leakage current which lead to minimize the power loss and prolong the battery life in idle mode. This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.
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Papers by bindu madhavi