Reliability enhancement via Sleep Transistors

IJMER

In the nanometer range design technologies static power consumption is very important issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards down in respect of size and achieving higher operating speeds. We have also considered these parameters such that we can control the leakage power. As process model design are getting smaller the density of device increases and threshold voltage as well as oxide thickness decrease to maintain the device performance. In this article two novel circuit techniques for reduction leakage current in NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a design model that has significant reduction in power dissipation during inactive (standby) mode of operation compared to classical power gating methods for these circuit techniques. The proposed circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier inverter leakage minimization techniques. All low leakage models of inverters are designed and simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average power, Leakage power, sleep transistor

2016

Low scaling technology makes a significant reduction in dimension and supply voltage, and leads to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed for low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In this paper, we combine these two generally separate addressed issues to reach a new low power high reliability flip-flop (LP-HRFF). LP-HRFF operates over 1GHz clock frequency and is structured based on an appropriate combination of dual interlocked storage cell, level converting techniques and clock signal controlled gates. The extensive simulations exhibit LP-HRFF has 0% single event upset rate against single transient events occurred on inputs and internal nodes and show the improvement of power consumption up to 42.8% and power delay product up to 24.6% compared with its counterparts. Furthermore, the simulation results approve the robustness and efficacy of the proposed flip-flop against process variations.

2012

2This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.

Low Power SRAMs have become a critical component of many VLSI chips. Power can be reduced by using either dynamic or static power reduction techniques. Power gating is one of the most effective static leakage reduction methods. In power gating sleep transistors are used. They disconnect the cell from power supply during sleep mode leading to 91.6% less static power dissipation but they also helps in reducing the dynamic power by reducing the power supply to the cell. In this paper the effect of sleep transistor in active mode is implemented and resulting SRAM is found to dissipate 32% less power than conventional SRAM.

2018

Flip flop are basic storage elements used extensively in digital system designs, which adopt intensive pipelining techniques and employ several FF-rich modules such as register files, shift registers, and FIFO. The power consumption of the FFs employed in a typical digital system design, along with that of clock distribution networks In this project, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master-slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual VDD design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power delay product (PDP).

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

Multi-threshold CMOS is a valuable leakage reduction method in circuit standby mode. Reducing leakage current through finegrain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improves circuit noise margins. In this paper, we first indicate the negligible dependence of ST size on the amount of leakage saving which makes the two-phase FGSTI reasonable based on our leakage current and delay models. Then we introduce a novel two-phase FGSTI technique: a) ST placement and b) ST sizing, which are formally modeled as two linear programming (LP) models respectively. Our experimental results show that the two-phase FGSTI technique can achieve 78.91%, 92.55%, 97.97% leakage saving when the circuit slowdown is 0%, 3%, 5% respectively. Comparing to the simultaneous ST placement and sizing method using mix integer linear programming (MLP) [1], our technique leads to on average 2% more leakage current reduction while at least 10X runtime saving since fewer variables and constraints with less approximation are used in the LP models. When the circuit slowdown is large enough to perform conventional fixed slowdown method, our technique can still achieve 75.48% ST area saving. Moreover, we show that when the circuit slowdown is 0%, it should be carefully considered to use FGSTI technique due to a large amount of leakage feedback gates.

FACTA UNIVERSITATIS Series: Electronics and Energetics, 2021

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures.

2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07, 2007

We study the problem ofreducing power during data-retention in a standby static random access memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be greater than a critical data retention voltage (DRV). Due to circuit parameter variations, the DRV for different cells on the same chip exhibits variation with a distribution having diminishing tail. For reliable data retention, the existing low-power design uses a worst-case technique in which a standby supply voltage that is larger than the highest DRV among all cells in an SRAM is used. Instead, our approach uses aggressive voltage reduction and counters the ensuing unreliability through a fault-tolerant memory architecture. The main results of this work are as follows: (i) We establish fundamental bounds on the power reduction in terms of the DRV-distribution using techniques from information theory. For the DRV-distribution of test-chip in [1], we show that 49% power reduction with respect to (w.r.t.) the worst-case is a fundamental lower bound while 40% power reduction w.r.t. the worst-case is achievable with a practical combinatorial scheme. (ii) We study the power reduction as a function of the block-length for low-latency codes since most applications using SRAM are latency constrained. We propose a reliable memory architecture based on the Hamming code for the next test-chip implementation with a predicted power reduction of 33% while accounting for coding overheads.