Redundant-via enhanced maze routing for yield improvement
Proceedings of the Asp Dac 2005 Asia and South Pacific Design Automation Conference 2005, 2005
Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the ... more Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with
Acm Transactions on Design Automation of Electronic Systems, 2009
In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As hi... more In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As highperformance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose a global router which has a strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is extended from BoxRouter 1.0, but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: node shifting for congestion-aware Steiner tree and robust negotiation-based A* search for routing stability. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) the widely used ISPD98 benchmark for the first time in the literature with the shortest wirelength. We further generate a set of harder ISPD98 benchmarks to push the limit of BoxRouter 2.0, and propose the hardened ISPD98 benchmarks to map state-of-the-art solutions for future routing research.
In this paper, we develop a multi-level physical hierarchy generation (mPG) algorithm integrated ... more In this paper, we develop a multi-level physical hierarchy generation (mPG) algorithm integrated with fast incremental global routing for directly updating and optimizing congestion cost during placement. The fast global routing is achieved by using a fast twobend routing and incremental A-tree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is also developed for placing objects with significant size variations. Experimental results show that, compared to GORDIAN-L , the wire length driven mPG is 3−6.5 times faster and generates slightly better wire length for test circuits larger than 100K cells. Moreover, the congestion driven mPG improves 50% wiring overflow with 5% larger bounding box wire length but 3 − 6% shorter routing wire length measured by graph based A-tree.
This paper presents a highly accurate yet efficient crosstalk noise model, the 2-¢ model, and app... more This paper presents a highly accurate yet efficient crosstalk noise model, the 2-¢ model, and applies it to interconnect optimizations for noise reduction. Compared to previous crosstalk noise models with similar complexity, our 2-¢ model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver) and the coarse distributed RC characteristics for the victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width. It is therefore very useful to guide noise-aware layout optimizations. In particular, we demonstrate its effectiveness in two applications: (i) optimization rule generation for noise reduction using various interconnect optimization techniques; (ii) simultaneous wire spacing to multiple nets for noise constrained area minimization.
In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incr... more In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast two-bend routing and incremental A-tree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is developed for placing objects with significant size variations. Experimental results show that, compared to GORDIAN-L, the wire length-driven MGP is 4-6.7 times faster and generates slightly better wire length for test circuits larger than 100 000 cells. Moreover, the congestion-driven MGP improves wiring overflow by 45%-74% with 5% larger bounding box wire length but 3%-7% shorter routing wire length measured by a graph-based A-tree global router.
7th International Symposium on Quality Electronic Design (ISQED'06), 2000
Process variation has become a major concern in the design of many nanometer circuits, including ... more Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is presented to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ignoring location dependent variation can cause a timing yield loss of 8.8% in a delay limited circuit, and the area can be improved by over 10% when the location dependent variation and residual random variation are understood and separated. Furthermore, under equivalent area, an interconnect pipeline optimized with only sizing changes may violate the slew constraint on over 50% of the nets, so location change is needed to best optimize these circuits.
As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) i... more As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140× speed-up even compared with accelerated ILP.
Chemical-mechanical polishing aware application-specific 3D NoC design
Proceedings of the International Conference on Computer Aided Design, Nov 7, 2010
ABSTRACT Three-dimensional (3D) integration with through-silicon vias (TSVs) is promising in the ... more ABSTRACT Three-dimensional (3D) integration with through-silicon vias (TSVs) is promising in the integration of many cores into a single chip. Network-on-chip (NoC) can efficiently manage the complicated 3D interconnections. However, irregular and dense TSV arrays used as vertical links in 3D NoC cause severe TSV height variation during silicon-thinning and chemical-mechanical polishing (CMP) processes. It may lead to TSV bonding failure between silicon layers. In this paper, we propose the first CMP-aware application-specific 3D NoC design that minimizes such TSV height variation and thus reduces the bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power consumption, and area. Our 3D NoC design assigns cores to proper silicon layers, determines the 3D NoC topology, allocates routing paths, and then floorplans all cores, routers, and TSV arrays in a CMP-aware manner. The key idea behind this 3D NoC design flow is to determine the CMP-aware 3D NoC topology where TSV arrays with low and uniform metal density are inserted between adjacent layers. Experimental results show that our CMP-aware 3D NoC design achieves, on average, 17.9% lower TSV height variation, 15% lower hop count, 2.3% shorter total wirelength, and 7.8% lower power consumption than the previous state-of-the-art 3D NoC designs.
Ieee Acm International Conference on Computer Aided Design Digest of Technical Papers, 2006
In this paper, we propose the first wire density driven global routing that considers CMP variati... more In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compact predictive CMP model with dummy fill, and validate it with extensive industry data. While wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. Therefore, wire density rather than congestion should be a unified metric to improve both CMP variation and timing. The proposed wire density driven global routing is implemented in a congestion-driven global router for CMP and timing optimization. The new global router utilizes several novel techniques to reduce the wire density of CMP and timing hotspots. Our experimental results are very encouraging. The proposed algorithm improves CMP variation and timing by over 7% with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router .
Interconnect Sizing and Spacing with Consideration of Coupling Capacitance
[18] B. Rohfleisch, B. Wurth, and K. Antreich, Logic clause analysis for delay optimization, in... more [18] B. Rohfleisch, B. Wurth, and K. Antreich, Logic clause analysis for delay optimization, in Proc. Design Automation Conf., June 1995, pp. 668672. [19] M. Schulz and E. Auth, Advanced automatic test pattern generation and redundancy identification techniques, in Proc. ...
Proceedings of the 43rd Annual Design Automation Conference, 2006
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniqu... more Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process parameters without considering process variations, due to prohibitive runtimes of lithography simulations across process windows. This is the first paper to propose a true process-variation aware OPC (PV-OPC) framework. It is enabled by the variational lithography modeling and guided by the variational edge placement error (V-EPE) metrics. Due to the analytical nature of our models, our PV-OPC is only about 2-3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (dosage and focus) during OPC. Thus our post PV-OPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.
Ieee Acm International Conference on Computer Aided Design Digest of Technical Papers, 2006
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable t... more Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.
17Th Asia and South Pacific Design Automation Conference, 2012
In this paper we present EPIC, a new generic and unified formulation to seamlessly combine the ad... more In this paper we present EPIC, a new generic and unified formulation to seamlessly combine the advantages of various types of lithographic hotspot detection techniques. With such formulation, we develop an efficient CAD flow and optimize it with quadratic programming techniques under industry-strength data at an advanced lithography node. After integrating various machine learning and pattern matching detection methods, we evaluate EPIC with a number of industry benchmarks under advanced manufacturing conditions. EPIC demonstrates so far the best capability in selectively combining the desirable features of various hotspot detection methods (3.5-8.2% accuracy improvement) as well as significant suppression of the detection noise (upto above 80% false-alarm reduction). These characteristics make EPIC very suitable for conducting high performance physical verification and guiding efficient manufacturability-friendly physical design. Pattern Matching Methods Good for detecting previously known types of hotspots Machine Learning Methods Good for detecting new/previously unknown types of hotspots A New Unified Formulation Good for detecting all types of hotspots with advantageous accuracy/false-alarm (The Meta-Classifier)
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