Voltage regulator

With the advent of smart grids, voltage fluctuation has increased, especially in active distribution networks with a high penetration of distributed energy resources and a large deployment of electric vehicles. In this context, on-load tap-changer (OLTC) distribution transformers have become a key component, mainly because they provide automatic voltage regulation capability. In order to maximise the lifetime of OLTC devices, the number of tap operations should be minimised, avoiding unnecessary changes, but ensuring the main requirement: to keep the voltage within the limits permitted. Therefore, when the automatic mode is active, the control policy followed by the automatic voltage regulator is decisive. This paper presents a novel form of functional approximation of these policies. Furthermore, by means of a unified framework, a methodology for the simulation of policies based on control theory is proposed. The unified framework has been validated using real data. The results con...

Recently, the wind power represents an important potential. In order to exploit this potential efficiently, the wind turbine must operate at different speeds when the wind speed changes. To deal with that, this study presents essentially the modeling and power control of Wind Energy Conversion Systems (WECS) based on Doubly Fed Induction Generator

This paper describes a complete digital PWM controller IC for high-frequency switching converters. Novel architecture and configurations of the key building blocks are A/D converter, compensator, and digital pulse-width modulator, are introduced to meet the requirements of tight output voltage regulation, high-speed dynamic response, and programmability without external passive components. The implementation techniques are experimentally verified on a prototype chip that takes less than 1 mm 2 of silicon area in a standard 0.5 digital complementary metal oxide semiconductor (CMOS) process and operates at the switching frequency of 1 MHz.

In this brief, a fully-integrated output-capacitorless digital low-dropout regulator (DLDO) is proposed utilizing the parallel proportional and integral (PI) controllers to achieve reduced voltage undershoot (∆V REG) and fast transient response time (T REC). The proposed PI controllers are implemented with the self-shifting bidirectional shift registers (SS-SRs) in coarse-fine dual loops along with complimentary PMOS and NMOS power transistors in coarse switch array and small-sized PMOS only transistors in fine switch array. Complimentary connections of PMOS and NMOS power transistors compensate for the load current (I LOAD) to reduce the ∆V REG , and smallsized PMOS reduces the steady-state voltage ripples. The proposed DLDO was designed and fabricated in a 65-nm CMOS process with an active area of 0.08 mm 2. Simulated results demonstrate that the proposed capacitor-less DLDO operates with an input voltage range of 0.7 V-1.2 V. For a load current step of 460 mA at V DD = 1.2 V, the proposed DLDO recovers a ∆V REG of 74 mV within 8 ns achieving an efficient load regulation of 0.004 mV/mA with a peak current efficiency of 99.58 %.

Under-Voltage Load Shedding (UVLS) protection of Electric Power Systems (EPS) is frequently used against Voltage Collapse (VC), however when there is automatic bus voltage regulation with excessive capacitive compensation, the UVLS scheme may not trip. In this case, load shedding must be based in a Voltage Collapse Proximity Indicator (VCPI). Many UVLS procedures may not be appropriate today. Approach: In order to elucidate the problem stated, several studies were carried out using MatLab/SimPowerSystems. In the first case, it was simulated a reduced electric system consisting of an infinite-bus feeding a load through a large impedance line. Two other cases were simulated now including a fixed capacitive impedance (representing a saturated SVC or similar) with 25 and 60 MVAr, both with a generator regulating the load bus voltage. Graphic curves representing the load bus voltage versus time were obtained with the application of a ramp power load. Results: In all cases the curves showed if there was sufficient time to command the UVLS scheme. The usual UVLS criteria failed for the third case. As the capacitive reactive power of the saturated compensation devices was increased, their equivalent capacitance, corresponding to the sum of maximum MVAr capacities, grows. The load demand increase, after MVAr saturation, can cause a voltage decrement which is too fast for UVLS adequate operation. Conclusion/Recommendations: Based in past experiences, any operator could be confident on existing UVLS protection of some area, but a VC can occur with the current situation without UVLS trip, as stated. It was suggested to check the current UVLS operation conditions, especially in areas where there was a growth of both load demand and reactive power resources. When UVLS method is found ineffective, then a suggestion is to replace it by a technique based upon some VCPI.

This paper presents study, design and control of Automatic generation control (AGC) and Automatic voltage regulator (AVR) for three area interconnected hydroelectric power system using PID controller. Due to the change of load as well as power flow in tie-line, the frequency, active power, voltage and reactive power are varying dynamically. So a robust control is required for maintaining the frequency and voltage profile within permissible value. AGC controls the frequency and active power flows in the system whereas the AVR maintains the voltage profile and reactive power flow in the system. This paper presents the application of PID controller for improving the performance characteristics of the controller (steady state error, settling time and overshoot value) by using Matlab/Simulink software.

A self-tuning method to determine the appropriate parameters of a proportional-integral-derivative controller for an automatic voltage regulator (AVR) system using a biogeography-based optimization (BBO) algorithm is proposed in this study. The BBO algorithm was developed based on the theory of biogeography, which describes migration and its results. We propose that the BBO algorithm has a high-quality solution and stable convergence characteristics, and thus it improves the transient response of the controlled system. The performance of the BBO algorithm depends on the transient response, root locus, and Bode analysis. Robustness analysis is done in the AVR system, which is tuned by an artificial bee colony (ABC) algorithm in order to identify its response to changes in the system parameters. We compare the BBO algorithm with the ABC algorithm, particle swarm optimization algorithm, and differential evolution algorithm. The results of this comparison show that the BBO algorithm has a better tuning capability than the other optimization algorithms.

This article presents an output-capacitorless lowdropout regulator (OCL-LDO), merging with a hybrid push-pull buffer. The hybrid push-pull buffer implements a dynamic and adaptive biasing push-pull gate driving circuit, achieving stability without needing a complex compensation circuit and external load capacitor. Our devised OCL-LDO can operate with a load current range of 0-30 mA, with a quiescent current of 7 µA at zero load current. The proposed OCL-LDO is fabricated in a 0.18-µm CMOS process with an active area of 0.03 mm 2. Measurement results show that with a load current stepping from 0-30 mA and an edge time of 100 ns, the output voltage undershoot is 0.14 V, with a corresponding recovery time of 150 ns. The measured load regulation is 0.207 mV/mA at a supply voltage of 1.15 V and a dropout voltage of 0.15 V.

This brief presents an output-capacitorless low-dropout
(OCL-LDO) regulator based on flipped-voltage-follower (FVF) and dual
pMOS pass transistors. An adaptive-compensation buffer (ACB) dynamically regulates the operation of the pass transistors. Specifically, when
the load current falls below 5 mA, only the smaller pass transistor
is activated; otherwise, both pass transistors are engaged, thereby
simultaneously mitigating the minimum load current requirement for
FVF architecture and extending the load current ranging from 0 to
30 mA while maintaining stability without an external load capacitor.
At 1.15-V supply voltage and 0-mA load current, the quiescent current
is 6 µA. The output voltage is 1.0 V with a dropout voltage of 0.15 V.
Measurements show that with a load current stepping from 0 to 30 mA
at an edge time of 100 ns, the output voltage undershoot is 0.2 V with a
recovery time of 200 ns while achieving a load regulation of 0.23 mV/V.
Our OCL-LDO is fabricated in a 180-nm CMOS with an active area of
0.031 mm2.

The project outlined in this report is the design, layout, and routing of a linear voltage regulator using Cadence VLSI (very-large-scale integration) software. The design specifications for this regulator are as follows: input voltage range of 5V + 1V, load current capabilities of 150mA, and output voltage range of 1.15V to 3.3V. Furthermore, the design of this circuit was broken into three main sub-circuits: an error amplifier, bandgap reference circuitry, and biasing circuitry for the bandgap. Together, these sub-circuits integrated to make the final design. Research for different topologies for a voltage regulator was done and the Brokaw bandgap reference circuit by Paul Brokaw was used for the reference voltage. The layout and routing of these sub-circuits was performed by breaking these sub-circuits into even smaller sub-circuits and routing these individually. In the end, the group was able to layout and route all of the sub-circuits. However, several DRC and LVS errors were encountered throughout the layout process. Main sources of errors were due to the bipolar junction transistors and resistors used in this design. To the best knowledge of the group, layout and routing of the bipolar junction transistors used in this design have never been attempted at California Polytechnic State University San Luis Obispo. Therefore, it was expected that the group ran into several problems with these devices and it is outlined in the report how some of these problems were resolved. From the final design, it was found that the voltage regulator that was created in Cadence has an output voltage of about 3.4V; 100mV more than the intended 3.3V, yielding a discrepancy of 3% from the design specifications. In regards to temperature, the design deviates about 85mV across the industrial temperature range of -40 to 100 . Another metric that was used to test the final design is the voltage deviation when the load current is swept from 0-150mA,which was found to be 170mV. It was found that the subcircuits created for this project performed fairly close to the intended purpose and therefore the design of the voltage regulator is seen as a success. Thus, the next step for this project will be to fix the DRC and LVS errors associated with BJTs and resistors. After that, extraction of the circuit should be done to determine the parasitic capacitance and inductance associated with this circuit. And finally, the GDSII file should be made to be sent to the chip manufacturer to tape-out the chip.

The project outlined in this report is the design, layout, and routing of a linear voltage regulator using Cadence VLSI (very-large-scale integration) software. The design specifications for this regulator are as follows: input voltage range of 5V + 1V, load current capabilities of 150mA, and output voltage range of 1.15V to 3.3V. Furthermore, the design of this circuit was broken into three main sub-circuits: an error amplifier, bandgap reference circuitry, and biasing circuitry for the bandgap. Together, these sub-circuits integrated to make the final design. Research for different topologies for a voltage regulator was done and the Brokaw bandgap reference circuit by Paul Brokaw was used for the reference voltage. The layout and routing of these sub-circuits was performed by breaking these sub-circuits into even smaller sub-circuits and routing these individually. In the end, the group was able to layout and route all of the sub-circuits. However, several DRC and LVS errors were ...

Digital LDOs enable on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Their design synthesizability with automatic placement and routing can enable per-core DVFS with quick design turnaround. To enable per-core voltage regulation, this paper showcases a digital LDO designed in 65nm CMOS process. The LDO exhibits core-level high load current driving capability of up to 125mA and a large voltage regulation range of 0.15V to 1.15V. The design employs asynchronous nonlinear control to achieve fast voltage droop mitigation under large load transient events. Measurements show a peak current efficiency of 99.9% and greater than 99.5% at a light load of only 4mA and 1nF load decoupling capacitance.

For obtaining efficient stability and good regulation of different devices in power system and industrial applications, automatic voltage regulators (AVR) are increasingly used. However, AVR without any controller will provides slow responses due to disturbance and may cause instability. In this study therefore, the objective is to consider a generator AVR system without PID controller and with PID controller, where the PID controller was tuned with a view for improving the response of the system and make comparison between the frequency deviation step response and the tuned PID controller block performance using linear block model and control techniques in MATLAB / Simulink environment, in which the design configuration and automated PID turning was used to tuned the PID controller for AVR system without and with PID controller for generator 1 and generator 2 respectively. Simulation results indicates that generator 1 shows higher frequency overshoot and oscillation as compared to generator 2, which shows low frequency overshoot and minimum oscillation. The performance response of the tuned AVR system in generator 2 with PID controller gives satisfactory settling time which was recorded at 1.44 second as against 5.54 second.

It employs a Thyristor-Controlled Reactor (TCR) and a Thyristor-Xchanged Capacitor (TSC) circuit to carry out responsive force compensation and voltage guidelines. The goal is to skillfully regulate the termination point estimate of the TCR/TSC branch using a brilliant artificial neural system (ANN) regulator in order to minimize the rms and THD values caused by dynamic voltage. The conventional TCR/TSC based SVC compensator's typical control architecture is tweaked somewhat to achieve this. We have shown that a thyristor-terminating plot with improved regulating powers may improve the force factor and overall symphony mutilation of the line voltage and current (THD), replacing the ANN regulator. Adequacy with variable straight loads is tested using these progressions. Models and loads that may be individually addressed by RLC circuits are considered for use in reenactment. As an example, for some line supply cases, using a state-of-the-art ANN regulator design in each half-pattern of the voltage source produces ideal advantages of terminating points satisfying state-of-the-art r.m.s estimation.

This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal⁻oxide⁻semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mV and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm².

Nowadays there is a development of the modern power system that led to an increasing in complexity in the study of power systems, and also brings new challenges to power system stability, and especially, to the aspects of transient stability and small-signal stability. This paper discuss an application of STATCOM( Static Synchronous Compensator) and SVC(Static Var Compensator), for effective improvement of power system stability by regulation of system voltage and the comparative study on different features of STATCOM and SVC is made through the review of papers and books such as v-i characteristic of STATCOM and SVC , dependence on common coupling point voltage of STATCOM vs SVC, response time of STATCOM vs SVC, system stability enhancement, V-Q characteristics of STATCOM and SVC cost of STATCOM vs SVC and voltage regulation capability. A comparative study on effectiveness of STATCOM and SVC in improvement of system stability is found that STATCOM is more effective than SVC to ensu...

Counterfeit electronics form a major roadblock towards a safe and successful economy. An increase in globalization has led to a major increase in the total number of counterfeit products all around the world. While several methods have been designed to detect counterfeits, very few of them have been applied to the system-on-chip (SoC). The influx of a variety of components in SoCs and the conglomeration of different types of properties makes it difficult to detect counterfeit SoCs. In this paper, we aim at detecting recycled counterfeit SoCs by evaluating the degradation of power supply rejection ratio (PSRR) of a low drop-out (LDO) regulator, a principal component of the power supply of the SoC. Since the power supply is a universal component in all SoCs, this method can be considered effective for most SoCs. We apply machine learning (ML) algorithms pertaining to the family of Gaussian mixture models to classify SoCs as recycled or new. Supervised and unsupervised ML algorithms show an accuracy of up to 90% and 74% of recycled detection. We also apply stand-alone LDO PSRR degradation to train the ML algorithm and test on PSRR from embedded LDOs in SoCs. This form of semisupervised ML performed well for our previous experiments of recycled detection with stand-alone LDOs but was not able to distinguish recycled SoCs from new SoCs, thus increasing the number of false detection.

This article presents the study of frequency regulation of a solar energy based two area integrated power system equipped with multi-staged PID & conventional PID controller. To optimize the parameters of the projected multi-staged PID controllers, invasive weed optimization algorithm (IWOA) is employed. A disturbance to the extent of 0.01 p.u. is injected to the control area-1 to examine the effectiveness of the controllers in maintaining the system stability. Comparison of the results with respect to the magnitude of oscillations and settling time indicates that the proposed multi-staged PID controller outperforms the classical PID controller. The projected multi-staged PID controller optimised by the aforesaid algorithm (IWOA) helps in attaining nominal values of the tie-line power & frequency deviations during large parametric variation of the system and variation of system condition. Robustness of the proposed control strategy is established under various conditions such as (i)...

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

This paper introduces a closed-loop control system for klystron modulators. The system is based on the discharge of a capacitor into a step-up voltage transformer and an active bouncer implemented with a multiphase buck converter. In order to obtain a constant Klystron voltage at the at-top, the active bouncer must compensate both the capacitor discharge and the pulse transformer characteristic. The proposed control includes an inner voltage regulation loop that controls the active bouncer output voltage and an outer one that controls the klystron voltage. The primary side current and main capacitor voltage are included in the regulation loops to simplify the controllers. Simulations demonstrate that the strategy adopted allows to obtain a precision better than 0:1% on a 110 kV klystron. Experimental tests have shown that the multiphase converter is able to track a high dynamics reference even under variable output voltage conditions.

The current work presents particle swarm optimization (PSO) calculation as an improvement strategy in the territory of tuning of the exemplary regulator introduced in automatic voltage regulator (AVR). The proposed PSO technique is applied with a mean to discover the ideal estimation of relative essential subsidiary (PID)controller gains with first request low pass channel introduced in the AVR. The voltage reaction of the AVR framework, as acquired by utilizing the proposed PSO based PID regulator with first request low pass channel, is contrasted with those offered by different calculations announced in the new cutting edge written works. The pith of the current work means that the proposed PSO procedure might be, effectively, applied for the AVR of force framework. Introduction In power generation system, automatic voltage controller (AVR) is used to keep up the terminal voltage of an alternator at a predefined level. The AVR controls the consistency of the terminal voltage by sh...

In this paper, it is presented a methodology for hree-phase distribution transformer modeling, considering several types of transformer configuration, to be used in algorithms of power flow in three-phase radial distribution networks. The paper provides a detailed discussion about the models and the results from an implementation of the power flow algorithm. The results, taken from three different networks, are presented for several transformer configurations and for voltage regulators as well.

Due to the huge amount of data available to buyers, the use of sophisticated algorithms can increase the revenue of ecommerce stores with modern recommender systems. The study was designed to investigate the impact of recommender systems on e-buyers online purchasing behaviors, and predict purchase patterns of buyers. The result of the study revealed how recommender systems affect shopping experience, increase sales for business owners and reach efficient product stocking and delivery. This research proposes an approach of increase in sales and the possibility of purchase prediction based on recommender systems. A survey of e-buyers was taken to determine the impact of recommender systems on past and future purchases. Results show that recommender systems improve shopping experience, increase purchase and can be a good tool to remind buyers of what they need to buy. It shows that recommender systems have the ability to predict what a buyer may be interested in purchasing. Based on t...

The paper is aimed at presenting the dynamic behaviour of a wind turbine equipped with a doubly fed induction generator (DFIG) in case of disturbances in the interconnected grid. A model of a DFIG is presented and adapted for analyzing the response of the wind generator to voltage control, frequency control, voltage sags and wind variations. Simulations, performed by a widely used power system analysis code, are reported and commented.

This paper describes an FPGA implementation of a fully digital clock and data recovery system (FD-CDR) with plesiochronous clocking. The design utilizes 51 FF's only. It does require, at worst, 2 preamble bits to get into lock. The extracted clock is not shifted as long as input data jitter is small (typically less than ±12.5%UI), thus, minimizing jitter in the extracted clock. Typically, for small input data jitter, the extracted clock shows an rms jitter of 51 ps which is mainly due to the 35.6 ps jitter (rms) of the system 100MHz-master clock. Besides, it can withstand an input data cycle-to-cycle jitter up to ±37.5% UI without getting out of lock. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. It is insensitive to long runs of transition-free data patterns. Besides, the extracted clock has a 50% duty cycle.

This paper describes a design of a fully digital clock and data recovery (CDR) system with plesiochronous clocking. Besides the well known advantages of digital implementations over analog ones in terms of robustness against process and temperature variations, scalability, compactness and low cost, the system also enjoys many features. It can withstand an input data cycle-to-cycle jitter up to ±37.5% UI. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. Furthermore, it needs only, at worst, three preamble bits to get into lock. It is insensitive to long runs of transition-free data patterns. The extracted data clock is not shifted as long as input data jitter is small (typically less than ±12.5%UI), thus, minimizing jitter in the extracted data clock. Besides, the extracted clock has a 50% duty cycle.

This paper is a simple and systematic approaches to the design and analysis a pulse width modulation (PWM) based sliding mode controller for buck DC-DC Converters. Various aspects of the design, including the practical problems and the proposed solutions, are detailed. However, these control strategies can't compensate for large load current and input voltage variations. In this paper, a new control strategy by compromising both schemes advantages and avoiding their drawbacks is proposed, analyzed and simulated.

This study evaluates and compares centralized and distributed reactive power compensation strategies using Static Var Compensators (SVCs) to enhance the performance of a high-voltage transmission system in the Caribbean region of Colombia. The methodology comprises four stages: system characterization, assessment of the uncompensated condition under peak demand, definition of four SVC-based scenarios, and steady-state analysis through power flow simulations using DIgSILENT PowerFactory. SVCs were modeled as Thyristor-Controlled Devices ("SVC Type 1") operating as PV nodes for voltage regulation. The evaluated scenarios include centralized SVCs at the Slack node, node N4, and node N20, as well as a distributed scheme across load nodes N51 to N55. Node selection was guided by power flow analysis, identifying voltage drops below 0.9 pu and overloads above 125%. Technically, the distributed strategy outperformed the centralized alternatives, reducing active power losses by 37.5%, reactive power exchange by 46.1%, and improving node voltages from 0.71 pu to values above 0.92 pu while requiring only 437 MVAr of compensation compared to 600 MVAr in centralized cases. Economically, the distributed configuration achieved the highest annual energy savings (36 GWh), the greatest financial return (USD 5.94 M/year), and the shortest payback period (7.4 years), highlighting its cost-effectiveness. This study's novelty lies in its system-level comparison of SVC deployment strategies under real operating constraints. The results demonstrate that distributed compensation not only improves technical performance but also provides a financially viable solution for enhancing grid reliability in infrastructure-limited transmission systems.

This paper discusses the merging of two optimization algorithms, atom search optimization and particle swarm optimization, to create a hybrid algorithm called hybrid atom search particle swarm optimization (h-ASPSO). Atom search optimization is an algorithm inspired by the movement of atoms in nature, which employs interaction forces and neighbor interaction to guide each atom in the population. On the other hand, particle swarm optimization is a swarm intelligence algorithm that uses a population of particles to search for the optimal solution through a social learning process. The proposed algorithm aims to reach exploration-exploitation balance to improve search efficiency. The efficacy of h-ASPSO has been demonstrated in improving the time-domain performance of two high-order real-world engineering problems: the design of a proportional-integral-derivative controller for an automatic voltage regulator and a doubly fed induction generator-based wind turbine systems. The results s...

This paper presents a detailed description of a synchronous generator excitation control system in the Palmar power plant, Uruguay. It also describes the most important aspects of the ATP modelling of the AC Voltage Regulator and Exciter. Some records of time response of the excitation control system to step change in input are included. Some results of ATP simulations of the field tests mentioned before are included. Finally a comparison was made between the obtained results from simulations and those obtained from field tests in order to validate the models developed.

This work presents the design of a master-slave sliding-mode control scheme for a modular inverter system composed of N parallel-connected Buck-based single inverters. AC output voltage regulation and balanced current--sharing among the single inverters is achieved by means of a set of switching surfaces and the corresponding sliding control laws. On the other hand, a set of design restrictions is established in terms of inverter parameters and AC output signal amplitude and frequency, this facilitating the subsequent design procedure. Simulation and experimental results for both resistive and nonlinear loads are provided to illustrate the application of the method.

An interleaving fixed switching frequency quasi-sliding control algorithm based on the Zero Average Dynamics (ZAD) approach is reported and applied to the design of a modular system of parallel-connected single-phase inverters. This approach is used in a laboratory prototype of three inverters with an FPGA control-based implementation embedding this algorithm. Experimental results are provided to illustrate the design features in terms of AC output voltage regulation, balanced current sharing among mismatched modules, interleaved fixed switching frequency operation and robustness with respect to load variations.

In this paper, we will learn about online shopping and consumer-shopping behavior related to it. We will learn how two major type of perceived risks i.e environmental and behavioral risk makes an impact upon the online behavior of a consumer. Online shopping potentially allows commercial Web providers to collect much more detailed consumer behavior information than they can from most physical shopping trips. Commercial Web providers can collect not only the same information available in most physical transactionsmdashidentity, credit history, employment status, legal statusmdashbut such additional information as electronic address, specific history of goods and services searched for and requested, nbspother Internet sites visited, and contents of the consumerrsquos data storage device. Secondary use of information captured online can more easily follow individual-level behavior. Highly touted by many Internet marketers is the idea that data specifically linked to a single identifiab...

The ever-changing use of electrical energy can affect the generator terminal voltage, this condition can result in a decrease in the reliability of the generator system. To maintain the reliability of the generator system, it is necessary to install a device capable of regulating the size of the terminal voltage or commonly called an auto voltage regulator (AVR). In this research, an AVR with Fuzzy Logic Control (FLC) method has been created which is able to regulate the generator terminal voltage. The results showed that the generator response with a 220V reference has a delay time = 0.45 s, rise time = 0.72 s, settling time = 1.15 s with a very small steady state error. AVR is able to improve the terminal voltage within ± 8 s when the generator is given a resistive load, and ± 6 s when the generator is given an inductive and capacitive load.

This paper explores the application of Superconducting Magnetic Energy Storage (SMES) based Dynamic Voltage Restorer (DVR) systems to improve voltage sag and swell issues in Sri Lanka's low voltage three-phase power system. Voltage sags and swells are critical power quality problems that can cause significant disruptions in both residential and industrial sectors. Voltage sags, often caused by short circuits, motor startups, or sudden increases in load, and voltage swells, typically resulting from abrupt load drops or capacitor bank switching, are common in industrial settings. The integration of SMES with DVR technology offers a promising solution by providing rapid and precise voltage correction. This study analyses the operation principle of the SMES-based DVR and designs the DVR output voltage control method using MATLAB SIMULINK [1]. Voltage sags and swells are detected using a power quality analyzer connected to the low-voltage three-phase power system. The collected data are used to simulate voltage sags and swells in MATLAB. The models of the SMES-based DVR are established, and simulation tests are performed to evaluate system performance. The results demonstrate significant improvements in voltage regulation, highlighting the feasibility and effectiveness of SMES-based DVR systems in enhancing power quality and reliability in Sri Lanka's low-voltage distribution network [2].

This paper presents a regenerative step-up/stepdown dc-dc zero-voltage-switching pulsewidth-modulation converter with active clamping. The switch losses are reduced due to the implementation of a simple active snubber circuit that provides soft commutation in all the switches of the converter. The theoretical analysis, basic equations, design methodology, and experimental results are shown in this paper. A control methodology to assure the output voltage regulation is also proposed. The main advantages of the proposed power converter are the small number of components, simplicity of the controller, robustness, small weight and size, and high efficiency.

This paper presents a regenerative step-up/stepdown dc-dc zero-voltage-switching pulsewidth-modulation converter with active clamping. The switch losses are reduced due to the implementation of a simple active snubber circuit that provides soft commutation in all the switches of the converter. The theoretical analysis, basic equations, design methodology, and experimental results are shown in this paper. A control methodology to assure the output voltage regulation is also proposed. The main advantages of the proposed power converter are the small number of components, simplicity of the controller, robustness, small weight and size, and high efficiency.

In an ac transmission line, it is possible to control the active and reactive power transfer independently, by adding series compensation voltage, in both magnitude and phase angle, to the line. A transmission line is connected in series to the Static Synchronous Series Compensator and a solid-state voltage source inverter with associated transformer. In line series, a SSSC imposes a variable amplitude nearly sinusoidal voltage. This injected voltage creates seriatim inductive or capacitive reactance with the line as it is approximately 90° from the line current. The modulated reactance produces this (simulated) varying reactance which modulates the electric power carried through the transmission line. This focus on preliminary research for controller design motivated this study to attempt further development of the SSSC and VSC models.

The study analyzes the use of Artificial Neural Networks (ANNs) in automatic voltage regulator (AVR) systems, focusing on their better control and tuning flexibility over PID controllers. This paper explores employing ANNs in AVR systems, which offer more control flexibility than PID controllers. ANN's input, activation function, and output parameters permit more accurate control but complicate customization. An AI-based optimization technique finds the best ANN improvements to improve transient response and system stability. This ANNbased methodology is compared to other AI methods' dynamic performance to prove its usefulness. Pole/zero and Bode analyses assess stability. Finally, the optimized AVR system's resistance to significant component time constant fluctuations shows enhanced performance and stability. Based on the ANN methodology, the proposed method achieves 59.82%, 56.09%, 14.94%, 34.24%, 35.70%, 21.64%, 12.0%, 41.33%, 14.84% and 15.17% less overshoot than differential evolution (DE).

The delay in the transition from transient to steady-state conditions in exciter field dynamics is identified as a key factor contributing to inefficiencies in maintaining a stable terminal output voltage in synchronous generators. This delay often results in significant overshoot in the generator's output voltage, negatively affecting the performance of connected loads such as electric motors. This study aims to develop and evaluate a control strategy based on Proportional-Integral-Derivative and Linear Quadratic Regulator (PID-LQR) models to mitigate this issue. A hybrid control system was designed to enhance voltage stability within the Automatic Voltage Regulator (AVR) of an exciterbased synchronous generator. Using MATLAB simulations, the proposed PID+I-LQR controller demonstrated a reduction in system overshoot from 60.9547% to 1.1524%, representing a 98.1% improvement in voltage stability. Comparative analysis with other control models confirmed the superior performance of the PID-LQR-based controllers in achieving smooth voltage response and convergence to a stable terminal voltage, with the exception of

In this paper, a simple single-stage ac/dc converter based on the flyback topology is presented. With a single switch, a fast-regulated output voltage is achieved and, although the line current is not sinusoidal, the converter complies with the Standard IEC 1000-3-2 about low frequency harmonics for a medium power range (50-500 W). The major advantages of this converter are the size and the efficiency. Design guidelines, analysis of the line current, and extensions to other topologies are analyzed. Experimental results are included in the paper.

— Clock and Data Recovery (CDR) circuits have been used extensively in the receivers of optical communication systems, and a variety of applications of inter and intra chip communications. The primary design/performance metrics of CDR circuits are clock jitter, lock range, acquisition time, power consumption, silicon area, and noise immunity. The main source of jitter is the power supply noise. The present paper investigates the effects of power supply noise on the jitter performance of the well known dual loop architecture of CDR system. In order to improve the jitter performance of the dual loop CDR system, the VCO alone is replaced by the self-biased Maneatis VCO which is well known for its immunity to power supply noise and process variations. The Maneatis VCO is widely used for microprocessors PLL systems but it is rarely used in CDR systems. The combination of the dual loop architecture and self-biased Maneatis VCO together provides the benefits of both schemes. Simulations we...

Clock and Data Recovery (CDR) circuits have been used extensively in the receivers of optical communication systems, and a variety of applications of inter and intra chip communications. The primary design/performance metrics of CDR circuits are clock jitter, lock range, acquisition time, power consumption, silicon area, and noise immunity. The main source of jitter is the power supply noise. The present paper investigates the effects of power supply noise on the jitter performance of the well known dual loop architecture of CDR system. In order to improve the jitter performance of the dual loop CDR system, the VCO alone is replaced by the selfbiased Maneatis VCO which is well known for its immunity to power supply noise and process variations. The Maneatis VCO is widely used for microprocessors PLL systems but it is rarely used in CDR systems. The combination of the dual loop architecture and self-biased Maneatis VCO together provides the benefits of both schemes. Simulations were ...