Proceedings of the 2009 12th International Symposium on Integrated Circuits, Dec 1, 2009
An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th In... more An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th International Symposium on Integrated Circuits, (pp.69-72) Singapore.
This paper presents a new RC relaxation oscillator for biomedical sensor interface circuit. A nov... more This paper presents a new RC relaxation oscillator for biomedical sensor interface circuit. A novel switch-capacitor based RC charging/discharging circuit is proposed to effectively improve the oscillator phase noise and power performance. The inverter-based comparator with replica biasing is employed and optimized to enhance the phase noise performance and to lower output dependence on the supply voltage variation. The oscillator's temperature insensitivity is also improved by resistor temperature compensation. The prototype RC relaxation oscillator circuit is designed in a commercial 65nm CMOS process. The post-layout simulation results showed 3.12 MHz output frequency, -112dBc/Hz phase noise at 100 kHz offset, and 16.6 µW power consumption under 1 V supply voltage. The frequency variation is ±0.294%/V for supply within 1 V to 1.6 V, and 11.31 ppm/°C for temperature across -40°C to 100°C. The overall circuit performance is compared favorably to the state-of-art designs, with an outstanding Figure of Merit (FOM) of 160.03 dBc/Hz at 100 kHz.
The manufacture and performance of diodes made in dielectrically isolated silicon substrates cont... more The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers
IEEE Transactions on Circuits and Systems I-regular Papers, 2013
This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifie... more This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rdorder harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs.
IEEE Transactions on Power Electronics, May 1, 2012
This paper presents a time-domain analysis of the intermodulation distortion (IMD) of a closed-lo... more This paper presents a time-domain analysis of the intermodulation distortion (IMD) of a closed-loop Class D amplifier with either 1 st -order or 2 nd -order loop filter. The derived expression for the IMD indicates that there exist significant 3 rd -order intermodulation products (3 rd -IMPs) within the output spectrum, which may lead to even greater distortion than the intrinsic harmonic components. In addition, the output expressions are compact, precise and suitable for hand calculation, so that the parametric relationships between the IMD and the magnitude and frequency of the input signals, as well as the effect of the loop filter design, are straightforwardly investigated. In order to accurately represent the IMD performance of Class D amplifiers, a modified testing setup is introduced to account for the dominantly large 3 rd -IMPs when the ITU-R standard is applied.
An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th In... more An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th International Symposium on Integrated Circuits, (pp.69-72) Singapore.
2022 IEEE International Symposium on Circuits and Systems (ISCAS), May 28, 2022
Mel frequency cepstral coefficient (MFCC) features are widely used in applications such as keywor... more Mel frequency cepstral coefficient (MFCC) features are widely used in applications such as keyword spotting, bearing fault detection and heart sound classification. This work proposes a low power MFCC engine that enables its use for battery-powered edge applications. Three hardware algorithm co-optimizations were adopted to achieve energy efficient MFCC hardware implementation. The approximated MFCC features due to the optimizations still allows good accuracy when deployed in several applications such as keyword spotting and bearing fault detection, reporting negligible accuracy drop of ≤1.5%. The proposed MFCC hardware consumes only 128nW at 0.3V supply and occupies only 0.08mm 2 in 40nm CMOS technology, which are 5× and 2.75× power and area reduction respectively when compared to the prior arts.
Activation functions such as hyperbolic tangent (tanh) and logistic sigmoid (sigmoid) are critica... more Activation functions such as hyperbolic tangent (tanh) and logistic sigmoid (sigmoid) are critical computing elements in a long short term memory (LSTM) cell and network. These activation functions are non-linear, leading to challenges in their hardware implementations. Area-efficient and high performance hardware implementation of these activation functions thus becomes crucial to allow high throughput in a LSTM accelerator. In this work, we propose an approximation scheme which is suitable for both tanh and sigmoid functions. The proposed hardware for sigmoid function is 8.3 times smaller than the state-of-the-art, while for tanh function, it is the second smallest design. When applying the approximated tanh and sigmoid of 2% error in a LSTM cell computation, its final hidden state and cell state record errors of 3.1% and 5.8% respectively. When the same approximated functions are applied to a single layer LSTM network of 64 hidden nodes, the accuracy drops by 2.8% only. This proposed small yet accurate activation function hardware is promising to be used in Internet of Things (IoT) applications where accuracy can be traded off for ultra-low power consumption.
2018 IEEE International Conference on Service Operations and Logistics, and Informatics (SOLI), 2018
The importance of internal network security has been on the rise due to the demand of businesses ... more The importance of internal network security has been on the rise due to the demand of businesses in organizations that deal complicated device connections in SCADA networks. Ideally, the firewall rule searching speed must be as effective as O(1) time complexity, to filter all network traffic regardless of the number of fields filtered and the number of firewall rules. This paper proposes an advanced firewall rules matching algorithm with designed hash table function. The proposed firewall rule matching algorithm based on our designed hash table function is able to achieve far better speed than other search algorithms. Additionally, our hash table-based algorithm shows a constant execution time regardless the number of firewall rules.
Analog Integrated Circuits and Signal Processing, 2018
The accuracy of an I/Q based biomedical impedance sensing sensor (IQBIS) suffers significantly fr... more The accuracy of an I/Q based biomedical impedance sensing sensor (IQBIS) suffers significantly from the PVT effects of the analog front-end, such as the amplitude errors of the stimulation signals, gain mismatches, amplitude and phase imbalances of in-phase (I) and quadrature (Q) signals, etc. These practical effects will severely impede the system performance if handled improperly. In this paper, the degradations of sensing performance by such imperfections are mathematically analyzed and quantified. Following theoretical studies, a training-based digitally controlled correction approach is proposed to finely alleviate these impairments. The performance of the proposed scheme had been verified using Simulink and MATLAB. With the proposed error correction scheme, the accuracy is improved by at least 17 times compared to that of the typical IQBIS, for both real and imaginary values of impedance. Thus, the proposed method is very useful for IQBIS, in resisting degradation in sensing accuracies due to the process-voltage-temperature (PVT) effects.
A rectifier-less ac-dc interface circuit for ambient energy harvesting from low-voltage piezoelec... more A rectifier-less ac-dc interface circuit for ambient energy harvesting from low-voltage piezoelectric transducer array
This paper presents a reference-voltage regulator free successive-approximation-register analog-t... more This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal⁻oxide⁻semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mV and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm².
The parasitic effects from electromechanical resonance, coupling, and substrate losses were colle... more The parasitic effects from electromechanical resonance, coupling, and substrate losses were collected to derive a new two-port equivalent-circuit model for Lamb wave resonators, especially for those fabricated on silicon technology. The proposed model is a hybrid π-type Butterworth-Van Dyke (PiBVD) model that accounts for the above mentioned parasitic effects which are commonly observed in Lamb-wave resonators. It is a combination of interdigital capacitor of both plate capacitance and fringe capacitance, interdigital resistance, Ohmic losses in substrate, and the acoustic motional behavior of typical Modified Butterworth-Van Dyke (MBVD) model. In the case studies presented in this paper using two-port Y-parameters, the PiBVD model fitted significantly better than the typical MBVD model, strengthening the capability on characterizing both magnitude and phase of either Y11 or Y21. The accurate modelling on two-port Y-parameters makes the PiBVD model beneficial in the characterization...
2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)
In this paper, a single-pole double-throw (SPDT) switching circuit that employs lateral metal-con... more In this paper, a single-pole double-throw (SPDT) switching circuit that employs lateral metal-contact micromachined switches fabricated on silicon-on-insulator (SOI) wafer is demonstrated to operate from DC to 6 GHz. The size of the fabricated SPDT switch is about 1.2 mm × 1.5 mm. The lateral metal-contact micromachined switches are formed on the quasi-finite ground coplanar waveguide (FGCPW) transmission lines and actuated by electrostatic force. The fabricated single-pole single-throw (SPST) lateral micromachined switch has an insertion loss of 0.2 dB and a return loss of 24 dB at 15 GHz. The isolation is 23 dB at 15 GHz. As for the fabricated SPDT switch, the measured insertion loss is below 0.75 dB and the return loss is higher than 19 dB at 5 GHz. The isolation at 5 GHz is above 33 dB. The threshold voltage of these switches is 22.5 volts, and these SOI switches are fabricated using deep reactive ion etching (DRIE) and shadow mask technology.
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008
In this paper, we present a new CMOS circuit design for increasing the threshold voltages (V T ) ... more In this paper, we present a new CMOS circuit design for increasing the threshold voltages (V T ) of MOSFETS to reduce power consumption. Using a single voltage source V DD , the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise V T . Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limited's (CHRT) 0.25-μm, 0.18-μm and Berkeley Predictive Technology Model's (BPTM) 90-nm processes showed good trade-offs between power savings and delay.
IEEE Microwave and Wireless Components Letters, 2015
This letter presents a temperature compensated oscillator for clock generation across a wide temp... more This letter presents a temperature compensated oscillator for clock generation across a wide temperature range. The proposed technique deploys the characteristics of the constant-biased varactors to nullify the overall oscillator's temperature coefficient (TC), thereby reducing the temperature drift effect on the oscillator frequency output. Fabricated on a 0.18-m CMOS technology, the proposed 2.09-GHz-gm-LC oscillator sees a mere 1.5-ppm/°C frequency drift from -20°C to 120°C. The oscillator consumes 10.9 mW at 1.4-V supply, with phase noise of -119.4 dBc/Hz at a 1-MHz offset. The demonstrated technique is useful for providing accurate clock for a variety of applications, including those operating in harsh environment.
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Papers by G. Ling