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Theory of Bit-Vectors

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lightbulbAbout this topic
The Theory of Bit-Vectors is a branch of computer science and mathematical logic that studies the properties and operations of bit-vectors, which are fixed-size sequences of binary digits. It focuses on the manipulation, representation, and analysis of these vectors in various computational contexts, particularly in formal verification and automated reasoning.
lightbulbAbout this topic
The Theory of Bit-Vectors is a branch of computer science and mathematical logic that studies the properties and operations of bit-vectors, which are fixed-size sequences of binary digits. It focuses on the manipulation, representation, and analysis of these vectors in various computational contexts, particularly in formal verification and automated reasoning.

Key research themes

1. How can computational efficiency be improved in processing bit-vectors, especially for matrix operations and cryptographic functions?

This theme focuses on algorithmic and hardware-oriented methods to optimize the computational cost related to bit-vector operations in applications such as neural networks, cryptographic S-Boxes, and bit-vector manipulation. Efficiency gains are crucial for embedded systems, real-time applications, and energy-constrained environments, where minimizing arithmetic operations and exploiting instruction-level parallelism are key.

Key finding: Introduces an algorithmic framework named linear computation coding that decomposes a constant matrix into codebook and wiring matrices with entries restricted to zero or signed integer powers of two. This allows... Read more
Key finding: Presents heuristic algorithms minimizing 8×8 cryptographic S-Boxes for bitsliced implementations using x86-64 SIMD instructions. It introduces three logical bases: universal (AND, OR, XOR, NOT), extended (including AND-NOT),... Read more
Key finding: Demonstrates that employing bit-level permutation instructions (Group operations, GRP) accelerates cryptographic algorithms in embedded environments, reducing footprint area, cost, and power consumption. The paper integrates... Read more
Key finding: Describes Boolector, an SMT solver optimizing the quantifier-free theories of bit-vectors combined with arrays by combining term rewriting, bit-blasting, and lemmas on demand. Boolector’s architecture efficiently simplifies... Read more

2. What formal decision procedures and solvers exist for the theory of fixed-sized bit-vectors and arrays, and how do they achieve completeness and efficiency?

This theme investigates formal theoretical frameworks, decision procedures, and solver architectures designed to decide satisfiability and optimize reasoning involving fixed-sized bit-vectors and extensional or non-extensional arrays. The insights focus on the combination of rewriting, bit-level and word-level reasoning, lemma generation, and solver integration strategies that guarantee soundness, completeness, and practical scalability in SMT contexts.

Key finding: Develops a decision procedure for quantifier-free fixed-size bit-vectors with composition and extraction, supporting integration into Shostak’s combination framework. The solver returns satisfiability or solved equations,... Read more
Key finding: Presents a comprehensive SMT solver design that integrates bit-vector rewriting, symbolic overflow detection, unconstrained variable propagation, and under-approximation techniques with lemma on demand generation for the... Read more
Key finding: Implements a decision engine combining bit-vector term rewriting and bit blasting with lazy lemma generation for arrays. The solver abstracts arrays initially and refines the model incrementally by adding theory lemmas when... Read more
Key finding: Introduces an internal consistency checking approach for all-different constraints (ADCs) over bit-vectors integrated directly within the SAT solver, avoiding costly external restarts. The method watches literals per... Read more
Key finding: Develops a novel decision procedure for the quantifier-free extensional theory of arrays that integrates lemma-on-demand generation in the accompanying theory solver rather than propositional abstraction. It proves soundness... Read more

3. How do structural properties of bit-vectors and specific code constructions inform error-correction and data compression within digital systems?

This theme examines mathematical properties of bit-vectors and permutations relevant for constructing error-correcting codes, data compression algorithms, and analyzing stochastic patterns in binary strings. These investigations provide insights into code size limits, statistical bit distributions, and connections between algebraic structures and coding theory, with applications in communication systems and memory bandwidth optimization.

Key finding: Introduces Bit-Plane Compression (BPC), a lightweight algorithm that increases effective memory bandwidth by transforming homogeneously typed data blocks with a Delta-BitPlane-XOR transform, followed by efficient encoding via... Read more
Key finding: Proposes a statistical method to construct block error-correcting codes using subsets of permutations characterized by minimum pairwise symbol Hamming distance. This approach yields large code sizes for short packets,... Read more
Key finding: Establishes that the first and second generalized Hamming weights (GHWs) of binary linear codes can be computed from graded free resolutions of monomial ideals associated with a Gröbner test set smaller than the complete set... Read more
Key finding: Analyzes the expected value of a random bit in binary words that forbid k consecutive ones, enumerated by k-step Fibonacci numbers. Proves that the bit frequency converges to a positive limit involving the generalized golden... Read more

All papers in Theory of Bit-Vectors

Propositional satisfiability (SAT) is a success story in Computer Science and Artificial Intelligence: SAT solvers are currently used to solve problems in many different application domains, including planning and formal verification. The... more
Model checking invariant properties of designs, represented as transition systems, with non-linear real arithmetic (NRA), is an important though very hard problem. On the one hand NRA is a hard-to-solve theory; on the other hand most of... more
Decision procedures for expressive logics such as linear arithmetic, bitvectors, uninterpreted functions, arrays or combinations of theories are becoming increasingly important in various areas of hardware and software development and... more
Incremental linearization is a conceptually simple, yet effective, technique that we have recently proposed for solving SMT problems over nonlinear real arithmetic constraints. In this paper, we show how the same approach can be applied... more
This paper introduces the 2019 version of ObjCP-FP, a novel Constraint Programming framework for floating point verification problems expressed with the SMT language of SMTLIB. SMT solvers decompose their task by delegating to specific... more
In recent years, string solvers have become an essential component in many formal-verification, security-analysis and bug-finding tools. Such solvers typically support a theory of string equations, the length function as well as the... more
Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a first-order formula with respect to some theory or combination of theories; Verification Modulo Theories (VMT) is the problem of analyzing the... more
We present new methods for solving the Satisfiability Modulo Theories problem over the theory of Quantifier-Free Non-linear Integer Arithmetic, SMT(QF-NIA), which consists in deciding the satisfiability of ground formulas with integer... more
This paper describes three variants of a counterexample guided inductive optimization (CEGIO) approach based on Satisfiability Modulo Theories (SMT) solvers. In particular, CEGIO relies on iterative executions to constrain a verification... more
We consider the problem of solving floating-point constraints obtained from software verification. We present UppSAT-an new implementation of a systematic approximation refinement framework [24] as an abstract SMT solver. Provided with an... more
Formal verification has increased efficiency by detecting corner case design bugs but it has also introduced new challenges when failures are detected. Once a counterexample is returned by a formal tool, the user typically does not know... more
Verification approaches based on constraint solvers are successfully applied in firmware and other low-level code that interfaces with hardware. While for proving safety of gate-level sequential circuits, it often suffices to bit-blast... more
Declarative models, in which conjunction and negation are freely used, are susceptible to unintentional overconstraint. Core extraction is a new analysis that mitigates this problem in the context of a checker based on reduction to SAT.... more
Incremental linearization is a conceptually simple, yet effective, technique that we have recently proposed for solving SMT problems over nonlinear real arithmetic constraints. In this paper, we show how the same approach can be applied... more
Abstract. Rarely verification problems originate from bit-level descriptions. Yet, most of the verification technologies are based on bit blasting, ie, reduction to boolean reasoning. In this paper we advocate reasoning at higher level of... more
Proof reconstruction is a technique that combines an interactive theorem prover and an automatic one in a sound way, so that users benefit from the expressiveness of the first tool and the automation of the latter. We present an... more
We present a new verification approach that applies aggressive program slicing and a proof-based abstraction-refinement strategy to enhance the scalability of bounded model checking of embedded software. While many software model-checking... more
Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a first-order formula with respect to some theory or combination of theories; Verification Modulo Theories (VMT) is the problem of analyzing the... more
Microcode is a critical component in modern microprocessors, and substantial effort has been devoted in the past to verify its correctness. A prominent approach, based on symbolic execution, traditionally relies on the use of boolean SAT... more
Rarely verification problems originate from bit-level descriptions. Yet, most of the verification technologies are based on bit blasting, i.e., reduction to boolean reasoning. In this paper we advocate reasoning at higher level of... more
This paper introduces the 2019 version of ObjCP-FP, a novel Constraint Programming framework for floating point verification problems expressed with the SMT language of SMTLIB. SMT solvers decompose their task by delegating to specific... more
Faculty of Science and Engineering Department of Computer Science Master of Science Predicting SMT solver performance for software verification by Andrew HEALY The approach Why3 takes to interfacing with a wide variety of interactive and... more
This volume contains the proceedings of SMT 2008, the 6th International Workshop on Satisfiability Modulo Theories, held in Princeton, New Jersey on July 7-8, 2008. The workshop was affiliated with the 20th International Conference on... more
MATHSAT is a long-term project, which has been jointly carried on by FBK-IRST and University of Trento, with the aim of developing and maintaining a state-of-the-art SMT tool for formal verification (and other applications). MATHSAT5 is... more
Formal checking at Register-Transfer Level (RTL) is currently a fundamental step in the design of hardware circuits. Most tools for formal checking, however, work at the boolean level, which is not expressive enough to capture the... more
In this paper we explain the design and preliminary implementation of a solver for the positive satisfiability problem of concepts in a fuzzy description logic over the infinite-valued product logic. The same solver also works for... more
We consider the problem of solving floating-point constraints obtained from software verification. We present UppSAT-an new implementation of a systematic approximation refinement framework [24] as an abstract SMT solver. Provided with an... more
A recent successful approach to security analysis reduces security questions about programs to constraint satisfaction problems in some formal logic. Automatic reasoners for that logic can then be used to solve those problems.
Generating the test inputs, that have high code coverage while minimizing the number of test inputs, is a practical but difficult problem. The application of symbolic execution in combination with SMT solvers gives a promising way to... more
Program Synthesis, which is the task of discovering programs that realize user intent, can be useful in several scenarios: discovery of new algorithms, helping regular programmers automatically discover tricky/mundane programming details,... more
Paper presented at Southern Africa Telecommunication Networks and Applications Conference (SATNAC) 2017, 3 - 10 September 2017, Freedom of the Seas, Royal Caribbean International, Barcelona, Spain
We consider the problem of solving floating-point constraints obtained from software verification. We present UppSAT-an new implementation of a systematic approximation refinement framework [21] as an abstract SMT solver. Provided with an... more
Bit-precise reasoning is important for many practical applications ofSatisfiability Modulo Theories (SMT). In recent years efficient approachesfor solving fixed-size bit-vector formulas have been developed. Fromthe theoretical point of... more
Bit-precise reasoning is important for many practical applications of Satisfiability Modulo Theories (SMT). In recent years, efficient approaches for solving fixed-size bit-vector formulas have been developed. From the theoretical point... more
Bit-precise reasoning is essential in many applications of Satisfiability Modulo Theories (SMT). In recent years, efficient approaches for solving fixed-size bit-vector formulas have been developed. Most of these approaches rely on... more
Bit-precise reasoning is essential in many applications of Satisfiability Modulo Theories (SMT). Most approaches for solving quantifier-free fixed-size bit-vector logics (QF BV) rely on bit-blasting. In previous work, we have shown that... more
The present paper describes a novel scheme for checking for potential defects in Lua programs, by using Bounded Model Checking (BMC). Such an approach, called BMCLua, translates a Lua program into an ANSI-C one, which is then verified by... more
We present DeepSAT, a novel end-to-end learning framework for the Boolean satisfiability (SAT) problem. Unlike existing solutions trained on random SAT instances with relatively weak supervisions, we propose applying the knowledge of the... more
Incremental linearization is a conceptually simple, yet effective, technique that we have recently proposed for solving SMT problems over nonlinear real arithmetic constraints. In this paper, we show how the same approach can be applied... more
MathSAT5 [1] is a lazy SMT solver [2] based on the DPLL(T) architecture [3], and it uses MiniSAT [4] as the underlying SAT solver. It supports most of the SMTLIB [5] theories and provides many SMT functionalities (e.g. unsatisfiable cores... more
Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a first-order formula with respect to some theory or combination of theories; Verification Modulo Theories (VMT) is the problem of analyzing the... more
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