System Generator

This research area investigates the development and application of generator systems embedded in object-oriented languages (notably Java) to automate the construction of parameterized, reusable digital designs for reconfigurable hardware such as FPGAs. The focus is on leveraging language features including partial evaluation, simulation, specialization, and hierarchical design composition to enhance productivity, portability, and quality of synthesized designs, while reducing design time compared to traditional schematic capture or HDL synthesis approaches.

This theme covers the use of formal models to describe system components, interactions, and configurations, which serve as the basis for automated generation of test cases, real-time operating systems (RTOSs), and system designs targeted at embedded and SoC systems. It emphasizes frameworks that enable precise behavioral specifications (e.g., using finite state machines), rich component modeling (including memories, registers, address translation), and scalable configuration, enabling high automation in RTOS generation and test-case derivation that balance ease-of-use, optimization, and configurability. The models abstract low-level details but support detailed system stimuli and validation, crucial for verifying complex multi-component embedded designs.

This research thread focuses on the development and implementation of hardware architectures and algorithms specifically optimized for FPGA execution, and the use of FPGA-tailored design methodologies such as System Generator extensions for analog/mixed-signal embedded systems, and hardware-accelerated algorithms like Support Vector Machines and image processing operations. These contributions emphasize efficient resource usage, reduced latency, high-operating frequencies, and improved real-time processing capabilities enabled by FPGA-specific architectures and co-design approaches.