X-Gen: a random test-case generator for systems and SoCs

IEEE Design & Test of Computers, 2004

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005., 2005

Design verification is crucial for successful systemson-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a novel technique to test the SoC at the system level using software application based programs. Our Software Application Level Verification Methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007

Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher potential to find faults in the design. We propose a model based test generation framework that generates tests for design fault classes inspired from software validation. There are two main contributions in this paper. Firstly, we propose a microprocessor modeling and test generation framework that generates test suites to satisfy Modified Condition Decision Coverage (MCDC), a structural coverage metric that detects most of the classified design faults as well as the remaining faults not covered by MCDC. Secondly, we show that there exists good correlation between types of design faults proposed by software validation and the errors/bugs reported in case studies on microprocessor validation. We demonstrate the framework by modeling and generating tests for the microarchitecture of VESPA, a 32-bit microprocessor. In the results section, we show that the tests generated using our framework's coverage directed approach detects the fault classes with 100% coverage, when compared to model-random test generation.

Testing of Communicating Systems, 1997

Application architectures have evolved to distributed architectures where applications are no longer seen as software blocks, but rather as cooperating software components, possibly distributed over the network. Some of the application's components may have already been thoroughly tested while others have not. This paper presents a pragmatic solution to component testing by means of controlling the composition process in order to identify global transitions that reflect the component's behaviour. The application of the proposed method is illustrated by an example based on the handling of a telephone call.

Proceedings of the 41st annual conference on Design automation - DAC '04, 2004

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.

1999

1 This paper presents a hierarchical test generation technique for embedded systems containing hardware and software. The technique is applied to the system-level specification of such systems. Different from the traditional approaches, hardware and software parts of an embedded system are handled in a uniform way. We will in particular show how the proposed technique can be applied at high levels of abstraction and how the software domain of the specification can also be successfully covered.

Journal of Systems Architecture, 2019

This paper describes a framework to verify the functional correctness of the Sam-sung Reconfigurable Processor, a dual-mode very-long instruction word (VLIW) and coarse-grained reconfigurable array (CGRA) processor integrated in smart-phones, cameras, printers, and SmartTVs. Reflecting the reconfigurable nature of the processor, the test generator constructs an architectural model directly from the processor's high-level hardware description files. Test programs are specified in a custom Constraint Specification Language that allows full coverage tests as well as verification of corner cases. Operations and operands are mapped to the heterogeneous processing elements of the CGRA using a guided place-and-routing algorithm. Requiring no explicit knowledge about the semantics of operations, the presented framework seamlessly supports custom ISA extensions. Experiments demonstrate that the framework is versatile, efficient, and quickly achieves a high coverage. In addition to detecting all randomly inserted faults, the generated test programs also exposed two yet unknown actual faults in the architecture.

2013

Creation of test programs and analysis of their execution is the main approach to system-level verification of microprocessors. A lot of techniques have been proposed to automate test program generation, ranging from completely random to well directed ones. However, no "silver bullet" has been found. In good industrial practices, various methods are combined complementing each other. Unfortunately, there is no solution that could integrate all (or at least most) of the techniques in a single framework. Engineers are forced to use a number of tools, which leads to the following problems:

2002

The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two phases: in the first, a library of code fragments (named macros) is generated by hand based on the knowledge of the instruction set, only. In the second phase, an optimization algorithm is run to suitably select macros and values for their parameters. The algorithm only relies on RT-level information, and exploits a suitable RT-level fault model to guide the test program generation. A major advantage of the proposed approach lies in the fact that it does not require any knowledge about the low level implementation of the processor. Experimental results gathered on an i8051 model using a prototypical implementation of the approach show that it is able to generate test programs whose gate-level fault coverage is higher than the one obtained by comparable gatelevel ATPG tools, while the computational effort and the length of the generated test program are similar. The method is thus suitable to be applied during the incoming inspection test phase performed on small processors, and for developing implementationindependent test suites for soft IP cores.

Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurable processor design. We report on experiments with two complex verification tasks. In both experiments, the model-based technology has achieved much higher coverage than standard verification tools and required considerably fewer engineering resources. We conclude that processor-oriented test generation technology addresses well the challenges of verifying automated hardware design.