Tales Pimenta

Followers

Following

Public Views

Interests

Uploads

Papers by Tales Pimenta

A Database Proposal for an Application Involving Industrial Networks for Industry 4.0 Concepts

This paper proposes to develop an application with the PROFINET network applied in the context of... more This paper proposes to develop an application with the PROFINET network applied in the context of the Industry 4.0. The proposal consists in collect data of an industry application, such as temperature and motor status, for instance, and then, by a tool developed in Python programming language, it is possible to monitor and control the magnitudes of the industrial process. The developed Database was used to monitor the variables in a PROFINET industrial network application.

Performance Analysis of Algorithms over FPGA for Removing Salt and Pepper Noise

IEEE Latin America Transactions, May 1, 2016

This paper shows the possibility to improve the accuracy of medical diagnosis on contaminated rad... more This paper shows the possibility to improve the accuracy of medical diagnosis on contaminated radiographic image with salt and pepper noise using FPGA-based filters. Investigation is carried out using filters described widely in the literature, such as Blur, Smooth and Gaussian linear filters and nonlinear median filter implemented on FPGA in an attempt to eliminate the noise. Implementations are checked on a development board with Spartan 6slx100fgg484-3 FPGA and a low-power optimized version Spartan 6slx100lfgg484-1l. The results are verified through the filtered images, resources consumption and the lowest response time. The implementation methodology uses model-based engineering involving MATLAB/Simulink and System Generator software using the XSGlmgLib library to perform co-simulation. The results show that the FPGA implementation of the median filter has a good tradeoff between resource consumption and noise removal efficiency.

Download

A review on principles, performance and complexity of linear estimation and detection techniques for MIMO systems

Frontiers in communications and networks, Feb 28, 2023

The advent of the fifth generation (5G) of mobile networks has introduced several new use cases t... more The advent of the fifth generation (5G) of mobile networks has introduced several new use cases that are pushing mobile networks in environments that are typically supported by wired technologies. The initial discussions around the sixth generation (6G) of mobile networks signalizes that different approaches are needed to address all contrasting requirements, where multiple-input multipleoutput (MIMO) technique stands as a key technology for most future wireless systems. In this review, we present an introduction on classical linear estimators and coherent detectors along with an innovative and accurate complexity formulation within a common framework, allowing a fair comparison and providing an initial guideline for researchers that are looking for a general view of the main techniques available for spatial multiplexing (SM)-MIMO detection and estimation.

Download

An interchip Power Line Communication

Dense wired networks, such as ultra-dense EEG network, comprised of 256 or 512 electrodes for tem... more Dense wired networks, such as ultra-dense EEG network, comprised of 256 or 512 electrodes for temporal and spatial analysis of the brain, demand a large amount of wiring. Instead of using a pair of wires for power supply and additional wiring for communication, the use of Power Line Communications (PLC) allows power and communication in a single pair of wires. In this project, we propose a transceiver (transmitter and receiver) 0.18µm CMOS technology, for a 1.8V power supply operating at 10 MHz. Simulations conducted on CADENCE (Virtuoso Analog Design Environment L Editing) demonstrate the circuit is capable of transmitting and receiving data properly.

A sub-threshold halo implanted MOS implementation of an electronic neuron

ABSTRACT This work describes a current mode implementation of Izhikevich neuron model designed wi... more ABSTRACT This work describes a current mode implementation of Izhikevich neuron model designed with 130 nm halo implanted devices structured within matrices of order m × n capable of substantially increasing output impedance while also improving mismatch and requiring a power supply of only 250 mV.

A CMOS voltage reference for ultra low-voltage applications

This work describes a CMOS voltage reference using only resistors and transistors working in weak... more This work describes a CMOS voltage reference using only resistors and transistors working in weak inversion, without any bipolar transistors. The circuit operation is similar to bandgap references, but the voltage reference is given by the threshold voltage of an NMOS transistor. The circuit was implemented in a standard 0.35 mum TSMC CMOS process. The circuit generates a reference of 514 mV for a power supply of just 900 mV and presents a 20 ppm/degC variation for the range of 0degC a 100degC.

Automated System for Testing Inductive Sensor

Comparative Study of Robotic Systems Based on Digital Twins

Uplink Dynamic Point Blanking Coordinated Multipoint Scheduler for IoT Integration in 5G Networks

When located at the cell edge, LTE network users suffer a severe loss of reception capacity due t... more When located at the cell edge, LTE network users suffer a severe loss of reception capacity due to interference from other cells. The development of 5G indicates that the dense deployment of small cells might worsen interference problems. Ever since this setback has been identified, several techniques emerged to mitigate the situation. Coordinated multipoint (CoMP) is one of these techniques, and dynamic point blanking (DPB) is one of the less complex forms of its implementation. In this work, a DPB scheduler is proposed to reduce interference in IoT scenarios using resources from a 5G network. Results show that the network aggregate throughput is increased while keeping fairness among the sensors when compared to a round-robin scheduler.

Decision-making system for detection of moving vehicles using a field programmable gate array combining conventional techniques of digital image processing with a fuzzy integral

Journal of Electronic Imaging, Jul 5, 2018

Abstract. Most of the methods surveyed for detecting moving objects through image processing in g... more Abstract. Most of the methods surveyed for detecting moving objects through image processing in general purpose processors (GPPs) presented an approach that did not allow successful implementation in field programmable gate array (FPGA). The correct classification of the pixels in these methods is directly related to the need for many resources in terms of memory due to the complex mechanism to get the reference image. Additionally, almost all the methods analyzed used only conventional techniques of digital image processing (DIP). Thus, we propose an approach that combines conventional techniques of DIP with fuzzy integral in a parallel processing aiming to improve the detection of moving vehicles. Hence, the proposed decision-making system seeks not to compromise results in terms of pixel classification even by implementing a simple modeling mechanism. Results in terms of occupied resource, maximum operating frequency, and pixel classification are verified in low-cost FPGA-based implementation. The proposed system processes the images in real-time and presents better pixel classification than just fuzzy decision-making.

Optimal design of VLSI structures with built-in self test based on reduced pseudo-exhaustive testing

A 0.25¿m CMOS Downconverter Mixer for 1.6GHz

This work shows the implementation of a CMOS double balanced mixer based in the Gilbert cell capa... more This work shows the implementation of a CMOS double balanced mixer based in the Gilbert cell capable of providing high conversion gain and high linearity. The mixer includes a common mode feedback circuit to keep a fixed DC level at the output and to maintain the transistors in the saturation, since the triode operation reduces the conversion gain. It uses

A self-biased operational amplifier of constant gm for 1.5 V rail-to-rail operation in 130nm CMOS

This article presents a rail-to-rail CMOS operational amplifier of constant gm. It offers simple ... more This article presents a rail-to-rail CMOS operational amplifier of constant gm. It offers simple topology and low power consumption. It uses a simplified shift level circuit at the input, a self-biased folded cascode as the intermediate stage and a class AB, or push-pull output stage to provide large gain. The amplifier, implemented in IBM 130nm CMOS technology, works on a 1.5V power supply voltage and consumes just 215μW, and offers a 125dB gain. A comparison to other work in the literature reveal a large gain, low power, rail-to-rail amplifier suitable to many applications.

Modificación automática de arquitecturas de módulos hardware de procesado de imágenes

El presente artículo describe el empleo del flujo de diseño basado en modelos para el desarrollo ... more El presente artículo describe el empleo del flujo de diseño basado en modelos para el desarrollo de bloques reconfigurables automáticamente para el procesado de imágenes sobre FPGA. Para ello se han concebido arquitecturas hardware que aprovechan características específicas de algunos algoritmos de procesado y que pueden ser modificadas a través de un novedoso procedimiento software. Este aspecto, unido a las restantes opciones de parametrización de los diferentes módulos, permite liberar al diseñador de los detalles específicos de las implementaciones hardware así como adaptar el consumo de recursos del FPGA a las necesidades de la aplicación. El proceso de reconfiguración automática se ilustra con el bloque de convolución genérico realizando comparaciones entre implementaciones de diferentes arquitecturas sobre un FPGA Spartan-6 LX45. Palabras claves: flujo de diseño basado en modelos, Xilinx System Generator, reconfiguración automática, XIL XSGImgLib This paper describes the use of model-based design flow in the development of self-configurable image processing blocks over FPGAs. For this, some generic hardware architectures has been created and modified using a novel software proceeding using the specific characteristics of the different processing algorithms. This aspect, in addition to others configuration options of the blocks, allows the adjustment the FPGA resources consumption for a specific application. Also the automatic reconfiguration process is analyzed for a generic convolution block making some architectural comparisons over a Spartan-6 LX45 FPGA.

Download

Introductory Chapter: RFID: A Successful History

InTech eBooks, Nov 29, 2017

Download

Implementation of a reconfigurable neural network in FPGA

This article proposes a new hardware implementation for a Reconfigurable Neural Network for syste... more This article proposes a new hardware implementation for a Reconfigurable Neural Network for systems in which the topology needs flexibility. The used architecture is a MultiLayer Perceptron, where the entry of a layer depends on the output of the previous layer. The approach allows flexibility in the number of network inputs, neurons, layers and in the activation function executed by neurons. Despite having been developed for FPGAs, the implemented circuit allows its implementation in ASIC, since it does not use proprietary internal blocks of the FPGA. By submitting the network to approximation tests, its operation and flexibility has been checked and validated.

Análise De Viabilidade Econômica Da Instalação Do Sistema Shore Power No Porto De Itaguaí Através Da Simulação De Monte Carlo

Editora Científica Digital eBooks, 2023

Download

Validation of a Signal Acquisition for Electrochemical Noise Corrosion Monitoring System

FPGA Implementation of Interval Type-2 Fuzzy System Based on Nie-Tan Algorithm

The Interval Type-2 Fuzzy Logic Systems – IT2FLS processors have been widely used in control proc... more The Interval Type-2 Fuzzy Logic Systems – IT2FLS processors have been widely used in control processes that analyzes uncertain information. The IT2FLS presents a superior performance compared to other methods for high uncertainty applications. In real-time control applications, circuit parallelism strategies increase the number of Fuzzy Logic Inference Per Second (FLIPS). This technique demands more hardware resources compared to sequential processing, which can make it difficult to use platforms that have resource limitations. This article presents an IT2FLS architecture implementation minimizes the use of parallel processing in the implementation in the inference engine and maintains the amount of FLIPS suitable for real-time applications. The proposed IT2FLS architecture is implemented in FPGA. It uses the type reduction circuits based on Nie-Tan algorithm. The hardware consists of two 8-bit inputs with four Gaussian membership functions for each one, sixteen rules and an 8-bit output with seven membership functions. The results of the FPGA implementation are compared with the same architecture implemented in Matlab® using the Toolbox for type-2 fuzzy.

Coexisting Analysis of 5G Networks with ISDB-T System in TV White Spaces

The efficient use of the electromagnetic spectrum becomes increasingly necessary due to the incre... more The efficient use of the electromagnetic spectrum becomes increasingly necessary due to the increase number of cellular devices. One possible solution is the opportunistic spectrum use in the VHF and UHF bands, allocated for television broadcasting. Therefore, it is necessary to evaluate the concurrent operation of broadcasting and mobile communication systems. This work aims to identify, analyze and measure the interoperability between those systems, by evaluating the feasibility of coexistence of different types of services. In this article, evaluations on two major candidates for the next cellular generation, the GFDM and the F-OFDM , operating along with the Integrated Services Digital Broadcasting Terrestrial – ISDB-T standard. The results show the flexibility of the GFDM and F-OFDM waveforms over the OFDM waveform, thus enabling opportunistic use of the spectrum over licensed and unlicensed users.

Tales Pimenta

Uploads

Papers by Tales Pimenta

Log In