Process Technology

This study used the case study approach to perform a longitudinal analysis of the implementation of skill-based pay plans in two different manufacturing plants in France within the same firm. The employees in both plants utilized the same process technology to produce cardboard boxes and packaging. Social regulation and bounded rationality theories were jointly used to explain the variations in pay plan design between the two plants. The results provide a deeper understanding of the implementation process and the variety of possible configurations of the design of skill-based pay. D

In this article we examine the use of two-level hybrid-material stamps and nanoimprint lithography (NIL) of poly(dimethylsiloxane) (PDMS) on glass substrates. A silicon/SU8 stamp manufacturing process has been developed, in order to combine nanometer and micrometer structures, thus avoiding complex deep etching processes. The stamp has been test printed in polymethyl methacrylate (PMMA) to demonstrate functionality. We describe polymer flow problems for imprinting large structures and identify optimized parameters, in accordance with previously published findings. The use of PDMS as imprint polymer was examined. Imprinting works well, however, large recovery after separation shrinks the micrometer channels substantially and renders the nanochannels useless. Glass substrates in combination with silicon stamps were used, evaluated and showed to work well at low temperature.

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

This paper presents limiting effect analysis of voltage scaling on Static Random Access Memory (SRAM) with process technology. The power reduction strategy utilize the property of standby circuit power reduction by reducing voltage swing available to cell by replacing ground and supply nodes by virtual ground and virtual supply nodes respectively. Important precaution to be taken in this method is complete charge removal from virtual nodes before next operation.

The Research and Information System for the Non-Aligned and Other Developing Countries (RIS) is an autonomous research institution established with the financial support of the Government of India. RIS is India's contribution to the fulfilment of the long-felt need of the developing world for creating a 'Think Tank' on global issues in the field of international economic relations and development cooperation. RIS has also been envisioned as a forum for fostering effective intellectual dialogue among developing countries. RIS is also mandated to function as an advisory body to the Government of India on matters pertaining to multilateral economic and social issues, including regional and sub-regional cooperation arrangements, as may be referred to it from time to time. RIS functions in close association with various governmental bodies, research institutions, academicians, policy-makers, business and industry circles in India and abroad. RIS has a consultative status with UNCTAD and NAM and has conducted policy research and other activities in collaboration with other agencies, including UN-ESCAP, UNCTAD, UNU, Group of 77, SAARC Secretariat, Asian Development Bank (ADB), The World Bank, and the South Centre.

This demonstration shows a prototype tool that projects an impression of how execution of a formally defined process will facilitate dispute resolution. Tool flexibility supports projecting the look and feel of a range of different processes, facilitating user evaluation of alternatives.

Management of business and software processes are areas of increasing interest, which evolved nearly independently from each other. In this article we present an approach to process management that has been applied to business and software processes and which, thereby, enabled cross-fertilization between both areas. The goal of this article is to report lessons learned in industrial as well as

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1's and 0's between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates. 1. INTRODUCTION In everyday life, we cannot be separated from the use of fixed and mobile telephone, sending and receiving data both at close and long distance, and various other types of communication. Utilization of IT in communication has spread to all areas of human life in the current era of information technology advances. Information sent over long distances has gone through various media that can naturally reduce the quality of information. One important factor in data and voice communications is the quality of information transmitted and arriving at the recipient. Ideally the information received is exactly the same as the information sent. In reality, however, this naturally occurring disorder cannot be eliminated at all but can be minimized. While the disturbance caused by human error may be suppressed or eliminated altogether. The use of Parity Generator is one way to minimize the errors of digital data on transmitted information by detecting unwanted digital data. There are two digital data formats used in the digital communication, data format with odd number of parity and data format with an even number of parity [1]. In a communication that uses the odd parity data format, all existing data is odd, so that if any of the data appears to have even parity, then this indicates a data error occurs. If this happens, then the recipient can recover the data that has the error either by repairing itself or by returning the data to the sender. To design a circuit layout to be implemented on an IC (Integrated Circuit), a tool is needed to realize the desired design. The layout of ICs is bound by a set of design rules [2], [7]. One of the tools for IC layout used for this Parity Generator is Tanner Tools that uses 0.7 micron technology. With 0.7 micron technology,

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En Quintana Roo, Chiapas, Tabasco, Campeche y Yucatán, así como en las Republicas centroamericanas, existe una enorme demanda insatisfecha de desarrollos tecnológico-energéticos a nivel familiar, comunitario, unidad productiva, y municipal.  Industria, comercio, turismo, agricultura, pesca y ganadería, comparten una auténtica “hambre” de energía adecuada, oportuna, confiable y a precios accesibles. Sin embargo, en toda esta basta región, no existe una sola empresa que se dedique, precisamente, al mantenimiento, basado en desarrollos tecnológicos “a la medida”, de sistemas de energía a menudo ya instalados pero operando deficientemente. Contribuir a la superación de este déficit, es el cometido del presente proyecto.  La propuesta persigue conformar la base tecnológica necesaria para el diseño y desarrollo de tecnologías de equipos, procesos y productos para la generación, transmisión y aplicación de energía proveniente de fuentes convencionales y alternas en Mesoamérica.

High Pressure Chemical Engineering Ph. Rudolf von Rohr and Ch. Trepp (Editors) 9 1996 Elsevier Science BV All rights reserved. 475 Extraction of Alkaloids from Lupinus a/bus sp. using Compressed Carbon Dioxide Femando J. Caetano*, M. Luisa Beirao da Costa**, M. Gabriela Bemardo-...

The study on risk classification was conducted on 183 hospitalized dengue patients (4 DF, 179 DHF). The severity of the risk criteria was determined based on three blood investigations, namely, platelet (PLT) count (less than or equal to 30 000 cells per mm 3), haematocrit (HCT) (increase by more than or equal to 20%), and either aspartate aminotransferase (AST) level (raised by 5-fold the normal upper limit) or alanine aminotransferase (ALT) level (raised by 5-fold the normal upper limit). The patients were divided into three groups based on their risk factors and the corresponding bioelectrical impedance analysis (BIA) (i.e. bioelectrical tissue conductivity (BETC) parameters), namely, resistance (R), phase angle (α), body capacitance (BC) and capacitive reactance (X c) were obtained and quantified. Using logistic regression analysis, X c was found to be the best predictor in predicting the risk and severity in dengue patients. Subsequent two-way analysis of variance (ANOVA) found that there was a statistically significant relationship between the group categories and the change in X c. Hence, it was shown that BIA, as reflected by the X c value, can effectively segregate between the lower-risk (female mean X c = 60.70Ω, range 58.09Ω-63.43Ω; male mean X c = 62.17Ω, range 59.92Ω-64.46Ω) and the higher-risk dengue patients (female mean X c = 43.99Ω, range 42.05Ω-45.97Ω; male mean X c = 50.65Ω range 49.25Ω-52.09Ω, with the control data ((female mean X c =69.41Ω, range 67.09Ω-71.74Ω, and (male mean X c =64.19Ω, range 61.37Ω-67.15Ω.
http://repository.searo.who.int/handle/123456789/16073
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