Process Technology

Oil is an important part of the Saudi economy. With the volatility of oil prices and the pressing needs of economic growth and development, the Saudi Arabian government has planned to diversify its sources of income. To this end, the majority of effort has focused on developing the non-oil export sectors, particularly in manufacturing. Despite government efforts to enhance the ratio of non-oil export to total exports, it remains weak, amounting to 15 per cent of total exports in 2010 (which compares unfavourably with the average for other Middle East and North Africa countries (MENA) which stood between 30-46 per cent in 2010). This research aims to provide a comprehensive assessment of non-oil exports and their financing in Saudi Arabia. This study uses unique, primary data, collected through a custom designed questionnaire and a unique sample of Saudi exports. There is currently no comparable database for Saudi firms, or for other MENA countries trying to engage in export diversification strategies. This dissertation comprises three main empirical parts which are; ownership structure and operations, finance, and business climate, respectively (chapters 3, 4 and 5). In the first, the econometric analysis shows multiple factors have a significant positive impact on export intensity, including: whether the firm is shareholding, the age of the firm, internationally and locally recognised quality certificate, length of export experience, supplies of domestic origin, independent retail stores, TV or radio advertising, a foreign language website and finally an export marketing plan. Regarding the impact of financial factors on exports at firm * source: (SDIF,2010) ** source: (SAMA,2011) By looking into the composition of the industry sector in Saudi Arabia, we can see that the 'other non-metallic minerals' sector heads all other sectors in terms of operating industrial units (771), representing 16.3 per cent of the total number of factories operating at the end of 2010. The other four sectors in the top five in terms of operating industrial units are the food and beverages products sector (15.9 per cent), rubber and plastic products (10.6 per cent), chemical materials and products (10.6 per cent), and the construction of metal products (7.4 per cent).

Complementary metal–oxide–semiconductor is widely used in manufacturing of IC. CMOS application is felt in microprocessor, microcontrollers, memories, many digital circuits. And are also used for several analog circuits. Due to high noise immunity and low static power consumption CMOS circuits are widely preferred with other logic circuits. CMOS circuits employ p-type and ntype MOSFETs to implement logic gates and other digital circuits. In this Paper we are designing Low power full subtractor using CMOS circuits, with various technologies compared with power dissipation individually.

Process technology and architecture innovation are the two engines that have fueled a spectacular advancement in FPGAs over the past 10 years. During this period, the price of FPGAs has been reduced with 2 orders of magnitude, the logic capacity of FPGAs has been increased with 2 orders of magnitude and the performance has been increased with one order of magnitude. Whereas ASICs buck the tide of processing technology, FPGAs ride the tide. Deep submicron effects are breaking the traditional modular design flow of traditional SOC architectures. A growing portion of the design time is spent on dealing with deep submicron effects, at the expense of the creative process of design authoring. Surveys show that, today, less than 20% of the design time, for complex SOCs, is spent on design authoring. Programmable FPGA platforms give designers the benefits of deep submicron but rather than focusing on getting the silicon to work, you can focus on getting the design to work. Today, several million logic gates can be implemented in FPGAs, as such covering the sweet spot of the ASIC market. By combining the programmable nature of the FPGA with advanced testing methodologies, the fitness of a specific piece of silicon can be guaranteed for a given application. The increased yield associated with the custom testing approach allows to further reduce price of large FPGAs with more than 80%. As a consequence, FPGAs are being used for ever higher product volumes. FPGAs, through their regular, parallel architecture and distributed memory organization can continue to take benefit of scaling dimensions by adding more parallel hardware and distributed memory. Von Neumann architectures, originating from the days when silicon area was very limited, have been dictating sequential programming models. Spatial computing, exploiting massive resources of parallel hardware will change the way we program future system platforms. We predict that FPGAs will become the heart of most systems over the next 5 years, replacing ASICs and processors as the fabric of choice.

The various digital electronic circuits like Microprocessors, Registers, and Memory modules are using flip flop as a basic unit for providing the proper processing of applications or working. This paper describes in detail about the importance of Flip Flops, and its layout design using CMOS technology. Using CMOS technology we can enhance the speed and reduce power consumption .There is various research works had been carried out throughout the world. Thus in this paper we are going through various steps as well as looking for various technology details in order to full fill our research work. KeywordsCMOS Technology, Digital Circuits, Tanner EDA, Flip Flop, Low Power

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Complementary metal-oxide-semiconductor is widely used in manufacturing of IC. CMOS application is felt in microprocessor, microcontrollers, memories, many digital circuits. And are also used for several analog circuits. Due to high noise immunity and low static power consumption CMOS circuits are widely preferred with other logic circuits. CMOS circuits employ p-type and ntype MOSFETs to implement logic gates and other digital circuits. In this Paper we are designing Low power full subtractor using CMOS circuits, with various technologies compared with power dissipation individually.

This paper describes in the introduction the actual research trends in the area of pharmaceutical technology and the impact of FDA's PAT (Process Analytical Technology) Initiative on this research field. These new FDA requirements concerning a science-based approach in the area of pharmaceutical formulations and processes will boost this research field in academia and industry. There is a special need for a research initiative in the field of pharmaceutical powder technology, which is the basis for ca. 80% of all drug delivery systems on the market, i.e. solid dosage forms. Pharmaceutical formulations are complex systems which are difficult to model and analyse. For this purpose special tools such as the percolation theory, concept of fractal dimensions, dielectric spectroscopy, etc. are necessary. In this context, typical results obtained with these novel tools are presented.

Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits.FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power. In this paper, we proposes a synchronous johnson counter by using FinFET Technology.FinFET logic implementation has significant advantages over static CMOS logic in terms of power consumption. The proposed counter was fabricated in 16nm FinFET technology in HSPICE.

Background The layout of an electronics circuit plays an important role in the design and usability of many products (Mihajlovic et al. 2007). In computers, communications, and many other systems, the flip-flops are fundamental building blocks. They are the important timing elements in digital circuits which have great impacts over power consumption and speed. The performance of Flip-Flop influence the performance of whole synchronous circuit,

Literature on project and knowledge management has examined knowledge management in projects, but the utilization of knowledge management in project marketing is still largely unexplored. This study examines the links between knowledge management and project marketing activities in a project where the seller wants to convince the potential buyer about a demanding investment project. An in-depth case study illustrates this in a situation hampered by a technical knowledge gap between the parties. The buyer is committed when they can trust the seller's capability to successfully accomplish the project. The seller must concretize and communicate its core and project-specific knowledge of technologies and customer needs through project marketing. A framework of and implications for knowledge management and project marketing activities in different project phases are presented. It is proposed that knowledge management is a pertinent tool for project marketing as it helps to understand the roles of different knowledge types.

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are

Abstract—In this paper an implementation of a new TFF using GDI technique for low-power and high-speed in order to achieve a PDP is presently while having a still low complexity. Simulation results using ADS 2008 show that the proposed flip flop has the least ...

Process Centered Environments (PCEs) are the most recent generation of environments supporting the software engineering process. They aim to drive and assist developpers in the application of software development methods, by exploiting an explicit representation of the process. Several PCEs have been developped, both as research project and commercial products. This paper makes a point of research works and research

The 32 nm process (also called 32 nanometer node) is the next step after the 45 nanometer process in CMOS semiconductor device fabrication. Like the 45 nm generation, the 32 nm node will take advantage of the performance tricks of the prior technology generation, including immersion lithography. The biggest change at 32 nm will be the introduction of high-k dielectrics and metal gates into production. The development of next 32 nm generation needs innovations on not only device structures, but also fabrication techniques and material selections.. This reduces the Power Dissipation and Leakage Current in the designing of any circuitry. The major sources of leakage current are the gate direct tunneling current, the subthreshold leakage and the reverse biased band-toband-tunneling junction leakage. To reduce total chip power, these leakage components must be suppressed. Here, for giving the advantages of 32nm scale technology 8-bit ALU was simulated on the different number of integration scale. The advantages of 32nm technology will be given over the other scaling technology. Result can be analyzed by simulating the schematic circuit with the help of CAD tools as DSCH & MICROWIND. This project work will help in giving the advantages of 32nm scale on comparing with the other counter parts and to provide the information about the advanced half node technology.

Improving city resilience is among the most challenging strategic goals for city administrators worldwide. To support their work, frameworks providing technical support and methodological guidance have been developed. Such frameworks define resilience improvement processes based on multidimensional resilience models to assess one city's resilience level, plus a collection of policies to increase such level in different dimensions. Although some frameworks include software tools to support the process, their scope is limited to a particular step of the process, and global management is still done manually, hindering agility in the process. In this paper, we present our work towards the digital transformation of a city resilience framework. The use of process technology to specify and enact the process is combined with the application of model-based development techniques to provide interoperability of the different framework tools. Our work is framed within a threeyear project started in mid 2020. Here, we report about the results of the first year of the project. Specifically, we describe the architecture of the solution proposed, as well as the major features of our approach.

The 32 nm process (also called 32 nanometer node) is the next step after the 45 nanometer process in CMOS semiconductor device fabrication. Like the 45 nm generation, the 32 nm node will take advantage of the performance tricks of the prior technology generation, including immersion lithography. The biggest change at 32 nm will be the introduction of high-k dielectrics and metal gates into production. The development of next 32 nm generation needs innovations on not only device structures, but also fabrication techniques and material selections.. This reduces the Power Dissipation and Leakage Current in the designing of any circuitry. The major sources of leakage current are the gate direct tunneling current, the subthreshold leakage and the reverse biased band-toband-tunneling junction leakage. To reduce total chip power, these leakage components must be suppressed. Here, for giving the advantages of 32nm scale technology 8-bit ALU was simulated on the different number of integration scale. The advantages of 32nm technology will be given over the other scaling technology. Result can be analyzed by simulating the schematic circuit with the help of CAD tools as DSCH & MICROWIND. This project work will help in giving the advantages of 32nm scale on comparing with the other counter parts and to provide the information about the advanced half node technology.

GENESIS is an Open Source distributed platform supporting cooperative software engineering. All requirements concerning cooperation, collaboration, and coordination have been derived from actual user needs, collected from some of the largest software development companies in the European scenario; moreover, an integrated approach, merging both process-centered and product-centered ones, has been adopted. In this paper we present such two basic facets of GENESIS, which constitute the main achievements of ...

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are

Improving city resilience is among the most challenging strategic goals for city administrators worldwide. To support their work, frameworks providing technical support and methodological guidance have been developed. Such frameworks define resilience improvement processes based on multidimensional resilience models to assess one city's resilience level, plus a collection of policies to increase such level in different dimensions. Although some frameworks include software tools to support the process, their scope is limited to a particular step of the process, and global management is still done manually, hindering agility in the process. In this paper, we present our work towards the digital transformation of a city resilience framework. The use of process technology to specify and enact the process is combined with the application of model-based development techniques to provide interoperability of the different framework tools. Our work is framed within a threeyear project started in mid 2020. Here, we report about the results of the first year of the project. Specifically, we describe the architecture of the solution proposed, as well as the major features of our approach.

Reduction of the size and the power consumption of the DFF, the component that has the largest area occupancy in the standard cell, is extremely useful for the reduction of the same characteristics in the entire chip. The proposed DFF is a semistatic configuration realizing True-Single-Phrase Clocking (TSPC). In comparison with the conventional circuit, this one is successful in reduction of power consumption and in improvement of circuit characteristics such as noise endurance. Also, even though the number of NMOSs is almost twice that of PMOSs, the lateral pitch is less than in the conventional small DFFs fabricated with the 0.25-2m SIMOX, bulk, and MT-CMOS low threshold process common layout, by virtue of a layout in which only the NMOSs are multistaged. The standard cell blocks designed with the proposed DFF are fabricated by a 0.25-2m SIMOX process. The power consumption is computed by measurement of the supply current. It is found that the power consumption is reduced by 23% on average in comparison with circuits using the conventional DFF.

Despite significant progress toward the commercialization of biobased products, today's biorefineries are far from achieving their intended goal of total biomass valorization and effective product diversification. The problem is conceptual. Modern biorefineries were built around well-optimized, cost-effective chemical synthesis routes, like those used in petroleum refineries for the synthesis of fuels, plastics, and solvents. However, these were designed for the conversion of fossil resources and are far from optimal for the processing of biomass, which has unique chemical characteristics. Accordingly, existing biomass commodities were never intended for modern biorefineries as they were bred to meet the needs of conventional agriculture. In this perspective paper, we propose a new path toward the design of efficient biorefineries, which capitalizes on a cross-disciplinary synergy between plant, physical, and catalysis science. In our view, the best opportunity to advance profitable and sustainable biorefineries requires the parallel development of novel feedstocks, conversion protocols and synthesis routes specifically tailored for total biomass valorization. Above all, we believe that plant biologists and process technologists can jointly explore the natural diversity of plants to synchronously develop both, biobased crops with designer chemistries and compatible conversion protocols that enable maximal biomass valorization with minimum input utilization. By building biorefineries from the bottom-up (i.e., starting with the crop), the envisioned partnership promises to develop cost-effective, biomass-dedicated routes which can be effectively scaled-up to deliver profitable and resource-use efficient biorefineries.

Process Centered Environments (PCEs) are the most recent generation of environments supporting the software engineering process. They aim to drive and assist developpers in the application of software development methods, by exploiting an explicit representation of the process. Several PCEs have been developped, both as research project and commercial products. This paper makes a point of research works and research

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (V dd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40 0 C to 100 0 C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at V dd of 1V and 0.5V, respectively.

Object-oriented specification mechanisms have become famous for modelling structure and behaviour together in terms of autonomous objects communicating via message passing. However, whereas most object-oriented specification methods are strong in modelling the local behaviour of single objects, they fall short on modelling the coordinated behaviour and collaboration of several objects together. The aim of this paper is to contribute to fill this gap. The paper reports on concepts, language constructs, and experiences with three collaboration formalisms in the area of object-oriented specifications.

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

Cuff electrodes are often used for interfacing nerves. Especially for small nerves, a new approach of flexible and light-weighted multichannel cuff electrodes with integrated cables has been developed using micro-chining technologies. Here, the process technology is shortly introduced. The results of in vitro test were discussed. In vivo implantations showed excellent properties of the electrode nerve interface.

This paper presents a design of fast voltage controlled delay element based on modified version of low noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to verify its performance.

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (V dd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40 0 C to 100 0 C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at V dd of 1V and 0.5V, respectively.

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (V dd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40 0 C to 100 0 C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at V dd of 1V and 0.5V, respectively.

Workflow is rapidly becoming a standard technology in the corporate computing environment. Workflow automates an actual business process, and as such must have a representation of that process. This paper questions how one arrives at the process to be represented. Collaborative Planning (CP) is presented as a way to discover and implement process representations regardless of the workflow system being used. The need for involving many people in the planning process is the result of a trend which is many decades old, and which is enjoying a new level of awareness due to the Business Process Reengineering movement. CP empowers users within a workflow environment to have control over their own processes. CP is defined and four general requirements for a CP tool are given. The benefits of this new technology are discussed; Regatta Technology is offered as an example of a CP tool.

Groupware aimed at coordinating the actions of people is faced with a dilemma. In order to support a group at work, the groupware must be configured into applications that accurately reflect how the group works. Yet, organizations are constantly changing both their structure and the way they work, leaving the groupware application inaccurate, or at least out of date. Implementers of groupware applications are finding that the cost of implementation comes not from the hardware or the software, but the effort needed to capture and codify their organizational processes, and then to maintain the applications to keep them up to date. This paper explores how the implementation of groupware is a collaborative activity. Methods to define processes, such as BPR, are group activities. A powerful way to solve this is to develop the groupware applications collaboratively. In a sense, this is groupware to help in the development of groupware. Four key capabilities are described that are needed t...

The aim of this work is to describe how learning and knowledge transfer mechanisms based on knowledge articulation and codification contribute to the development of organizational capabilities in software. The study focuses on client-specific and process capabilities. Results were obtained through a case study involving two partner companies in an inter-organizational project to develop an integrated information management and technology system. Evidence revealed investment and organizational efforts focused on knowledge articulation practices and activities to develop client-specific capabilities, as well as knowledge codification practices and activities to develop process capabilities. We also identified three factors that influenced software professionals’ choice of the respective mechanisms (knowledge articulation and codification) namely: the sharing context, absorptive capacity and task complexity.

The Research and Information System for the Non-Aligned and Other Developing Countries (RIS) is an autonomous research institution established with the financial support of the Government of India. RIS is India's contribution to the fulfilment of the long-felt need of the developing world for creating a 'Think Tank' on global issues in the field of international economic relations and development cooperation. RIS has also been envisioned as a forum for fostering effective intellectual dialogue among developing countries. RIS is also mandated to function as an advisory body to the Government of India on matters pertaining to multilateral economic and social issues, including regional and sub-regional cooperation arrangements, as may be referred to it from time to time. RIS functions in close association with various governmental bodies, research institutions, academicians, policy-makers, business and industry circles in India and abroad. RIS has a consultative status with UNCTAD and NAM and has conducted policy research and other activities in collaboration with other agencies, including UN-ESCAP, UNCTAD, UNU, Group of 77, SAARC Secretariat, Asian Development Bank (ADB), The World Bank, and the South Centre.

Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V 2 dd and static power is proportional to V dd , lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC (90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (V dd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40 0 C to 100 0 C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at V dd of 1V and 0.5V, respectively.

Clock overlap is an important issue in the design of sequential circuits and is typically avoided. In this paper we present a new power-efficient edge-triggered D flipflop in which we have benefited from the overlap period of the clock signal. The design procedure of the proposed D flip-flop is presented. The performance of the flip-flop is compared with several state of the art flip-flops in a shift register and a pipeline adder in 0.18µm CMOS technology. The proposed flip-flop has the lowest power-delay-product and consumes less area compared to others.

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x18...

In this article we examine the use of two-level hybrid-material stamps and nanoimprint lithography (NIL) of poly(dimethylsiloxane) (PDMS) on glass substrates. A silicon/SU8 stamp manufacturing process has been developed, in order to combine nanometer and micrometer structures, thus avoiding complex deep etching processes. The stamp has been test printed in polymethyl methacrylate (PMMA) to demonstrate functionality. We describe polymer flow problems for imprinting large structures and identify optimized parameters, in accordance with previously published findings. The use of PDMS as imprint polymer was examined. Imprinting works well, however, large recovery after separation shrinks the micrometer channels substantially and renders the nanochannels useless. Glass substrates in combination with silicon stamps were used, evaluated and showed to work well at low temperature.

Process Centered Environments (PCEs) are the most recent generation of environments supporting the software engineering process. They aim to drive and assist developpers in the application of software development methods, by exploiting an explicit representation of the process. Several PCEs have been developped, both as research project and commercial products. This paper makes a point of research works and research challenges. It identifies 8 PCEs and a list of general requirements selected regarding actual software ...

Object-oriented specification mechanisms have become famous for modelling structure and behaviour together in terms of autonomous objects communicating via message passing. However, whereas most object-oriented specification methods are strong in modelling the local behaviour of single objects, they fall short on modelling the coordinated behaviour and collaboration of several objects together. The aim of this paper is to contribute to fill this gap. The paper reports on concepts, language constructs, and experiences with three collaboration formalisms in the area of object-oriented specifications.

Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers. .

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are

This demonstration shows a prototype tool that projects an impression of how execution of a formally defined process will facilitate dispute resolution. Tool flexibility supports projecting the look and feel of a range of different processes, facilitating user evaluation of alternatives.

This demonstration shows a prototype tool that projects an impression of how execution of a formally defined process will facilitate dispute resolution. Tool flexibility supports projecting the look and feel of a range of different processes, facilitating user evaluation of alternatives.

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1's and 0's between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates. 1. INTRODUCTION In everyday life, we cannot be separated from the use of fixed and mobile telephone, sending and receiving data both at close and long distance, and various other types of communication. Utilization of IT in communication has spread to all areas of human life in the current era of information technology advances. Information sent over long distances has gone through various media that can naturally reduce the quality of information. One important factor in data and voice communications is the quality of information transmitted and arriving at the recipient. Ideally the information received is exactly the same as the information sent. In reality, however, this naturally occurring disorder cannot be eliminated at all but can be minimized. While the disturbance caused by human error may be suppressed or eliminated altogether. The use of Parity Generator is one way to minimize the errors of digital data on transmitted information by detecting unwanted digital data. There are two digital data formats used in the digital communication, data format with odd number of parity and data format with an even number of parity [1]. In a communication that uses the odd parity data format, all existing data is odd, so that if any of the data appears to have even parity, then this indicates a data error occurs. If this happens, then the recipient can recover the data that has the error either by repairing itself or by returning the data to the sender. To design a circuit layout to be implemented on an IC (Integrated Circuit), a tool is needed to realize the desired design. The layout of ICs is bound by a set of design rules [2], [7]. One of the tools for IC layout used for this Parity Generator is Tanner Tools that uses 0.7 micron technology. With 0.7 micron technology,

The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of the circuit is also reduced. The analyses of the circuit is done using Cadence virtuoso tool with 45n technology.

In this paper, a new approach is taken to design
sense amplifier based flip-flop (SAFF) to improve
performance of this device which is most frequency used in
memory devices. With this, problem of cross coupled SR
latch in existing SAFF (NAND latch) is removed. The new
flip-flop uses a new output stage latch topology using GDI
technique that significantly reduces power consumption and
has improved power-delay product (PDP). Various
topologies along with their layout simulations have been
compared with respect to the number of devices, power
consumption, power-delay product, temperature
sustainability in order to prove the superiority of proposed
design over existing conventional CMOS-NAND design.
The simulation has been carried out on Tanner EDA tool on
BSIM3v3 45nm technology.

As the channel length of MOSFETs is scaling down, the Power dissipation of the SRAM cells become the major concern for future technology. In this paper, stable SRAM cell's power dissipation reduction in 6T static random access memory (SRAM), is described by using dynamic self-controllable voltage level (SVL) switch. Total power dissipation is reduced by 74/% and 84% at 1.2 volt and die area is increased by 36% and 69% from 120nm to 65nm technology respectively. The schematic and layout are drawn on 120nm and 65nm technology file on a Dsch tool and their analysis is done on a Microwind 3.1 tool and BSIM simulator.