Papers by Abolfazl Bijari
Rule discovery for pseudorandom number generator based on cellular automata
2010 International Symposium on Information Technology, 2010
ABSTRACT Since the behavior of cellular automata strongly depends on their rules, it is essential... more ABSTRACT Since the behavior of cellular automata strongly depends on their rules, it is essential to find appropriate rules for a specific application. This paper concern with rule discovery in cellular automata pseudorandom number generators. In this paper, we propose a new criterion to find high quality rules for CA randomizers. We make use of the proposed criterion to find appropriate rules of radius two and to construct a CA randomizer based on one-dimensional non-uniform cellular automata. Moreover, this paper presents and proves some new observations about the relationship between behavior of a CA and its size.
An ultra‐low‐power low‐noise amplifier using a combination of current reuse and self‐forward body bias techniques for biomedical applications
International journal of circuit theory and applications, Jun 16, 2024
A new approach to multi-objective optimization of a tapered matrix distributed amplifier for UWB applications
Neural Computing and Applications
A New Microstrip Dual-Band Bandpass Filter using Optimum Coupling Matrix for WLAN Applications
This paper describes the design of a new dual-band bandpass microstrip filter (DB-BPF) with a com... more This paper describes the design of a new dual-band bandpass microstrip filter (DB-BPF) with a compact size at central frequencies of 2.4- and 5.2-GHz and fractional bandwidth (FBW) of 4% for wireless local area network (WLAN) applications. The design of the DB-BPF is based on the coupling matrix by employing the optimization of its entries to generate the desired structure. The proposed DB-BPF uses half wavelength ($\lambda/2$) resonators. In order to minimize the size, conventional $\lambda/2$ resonators are substituted by folded $\lambda/2$ resonators. DB-BPF is designed and simulated on RT 4003 substrate. For 2.4/5.2 GHz bands simulation results show an insertion loss of 0.8/1.3 dB, with the S11 of lower than −10 dB, and FBW of 4%, respectively. Moreover, the proposed filter exhibits good performances including high isolation between two close passbands and high band selectivity. The overall size of the proposed DB-BPF is $30\ \text{mm}\times 40\ \text{mm}$ approximately.
DOAJ (DOAJ: Directory of Open Access Journals), Jul 1, 2021
Background and Objectives: Comparators play a critical role in the analog to digital converters (... more Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). Therefore, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect the comparator's performance. In low power applications, power consumption and delay are the critical concerns that should be minimized to obtain better performance. In this work, a low-power and highspeed comparator has been proposed, which is suitable for applications operating at a low power supply. Methods: Based on the conventional structure of the comparator, some modifications are implemented to achieve better performance in terms of power consumption and delay. Additionally, the proposed structure gives great performance when the difference of inputs is very small. To verify the proposed structure, it is designed and simulated in a 0.18 μm CMOS technology with a power supply of 1 V and sampling frequency of 2 MHz. Results: To draw a fair comparison, the conventional and proposed structure is simulated in equal circumstance. The size of transistors is designed with appropriate W/L ratios to achieve appropriate performance. The proposed structure not only reduces the power consumption by 44%, but also it decreases the delay by 9.1%. The power consumption of the proposed structure is around 0.12 µw. The total occupied area by the proposed structure is approximately 127.44 µm 2. Conclusion: In this paper, we presented a delay analysis for the proposed dynamic comparator. In addition, based on theoretical analyses, a new dynamic comparator consumes less power and operates faster compared with the conventional structure. The simulation results verify the theoretical analysis.
نشریه مهندسی برق و الکترونیک ایران, Jul 1, 2022
Circuits Systems and Signal Processing, Jun 15, 2020
This paper presents a down-conversion active mixer with improved performance for direct conversio... more This paper presents a down-conversion active mixer with improved performance for direct conversion receivers in wireless local area networks. The effect of negative admittance on the Gilbert cell mixer performance is investigated in terms of flicker noise, conversion gain, and linearity. The proposed negative admittance is implemented using a modified negative capacitance connected in parallel to a negative resistance, which exhibits a high degree of freedom to achieve high negative capacitance along with low negative resistance. The proposed mixer is designed and simulated using TSMC 0.18 µm CMOS technology in Cadence Spectre-RF at the input frequency of 2.4 GHz and intermediate frequency of 10 MHz. Post-layout simulation results show using the negative admittance can improve the flicker noise more than 16.7 dB at the frequency of 1 kHz. The proposed mixer exhibits a conversion gain of 19.3 dB and a flicker noise corner frequency of 5 kHz. The double-side band noise figure is 7.57 dB at the output frequency of 10 MHz, and the third-order intermodulation intercept point (IIP3) is − 7.5 dBm. The power dissipation is 13.6 mW from the power supply of 1.8 V. Moreover, the linearity of the proposed mixer can be enhanced by choosing the proper values for transconductance of switching quad and negative resistance so that it achieves the IIP3 of + 7.9 dBm with the conversion gain of 7.6 dB.
A new compact, wide bandwidth <scp>dual‐passband</scp> microstrip filter based on <scp>dual‐mode stepped‐impedance‐resonators</scp>
International Journal of Rf and Microwave Computer-aided Engineering, Oct 14, 2022
Power efficiency enhancement analysis of an inverse class D power amplifier for NB-IoT applications
Analog Integrated Circuits and Signal Processing, Feb 17, 2021
The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Freque... more The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high efficiency fully integrated inverse class D power amplifier for the narrowband Internet of Things (NB-IoT) applications. In this design, the PA's power added efficiency (PAE) is improved by inserting two auxiliary PMOS transistors into the conventional topology of class D−1 PA, and the chip area is reduced by proper selection of the RF choke. An on-chip balun is designed to combine the output power of the two transistors, while its primary equivalent inductor resonates with a capacitor at the fundamental frequency. Based on simulation results, the proposed PA achieves 16.5 dBm output power with a peak power added efficiency (PAE) of 51.3%, while operating from a 1-V supply. Moreover, the proposed PA demonstrates the power gain of 21.6 dB and drain efficiency of 57% at the frequency band of 1.85–1.91 GHz. By using 180 nm TSMC technology, the proposed PA occupies a total chip area of 1.19 mm2 (0.85 mm × 1.4 mm), including pads.
A Low Power, High Gain 2.4/5.2 GHz Concurrent Dual-Band Low Noise Amplifier
This paper introduces a high gain and low power concurrent dual-band low-noise amplifier (LNA) op... more This paper introduces a high gain and low power concurrent dual-band low-noise amplifier (LNA) operating in the 2.4/5.2-GHz which can be used for wireless local area network (WLAN) applications. The proposed dual-band LNA consists of a wideband LNA and notch filters. The wideband LNA employs current-reused technique to reduce power consumption and provide flat gain over wide bandwidth. By applying notch filters at the first stage output and the second stage input of the wideband LNA, the dual-band frequency response is formed. The dual-band LNA has been designed and simulated in RF-TSMC 0.18µm CMOS technology by Advanced Designed System (ADS). The power consumption is 2.25 mW in both bands with 1.8 V supply voltage. At 2.4 GHz, simulation results exhibit a noise figure (NF) of 1.8 dB, a power gain (S21) of 15.9 dB and an input return loss (S11) of -14 dB. In addition, it features a NF of 2.7 dB, a power gain of 14.3 dB and an input return loss of -12.8 dB at 5.2 GHz.
A new compact microstrip dual bandpass filter using stepped impedance and <i>λ</i> /2 bended resonators
International Journal of Rf and Microwave Computer-aided Engineering, Feb 1, 2021
In this paper, a compact dual‐band bandpass filter (DB‐BPF) is implemented by using a pair of cou... more In this paper, a compact dual‐band bandpass filter (DB‐BPF) is implemented by using a pair of coupled stepped impedance resonators (SIRs) and a pair of λ/2 bended resonators for the modern wireless communication systems such as WiMAX and WLAN (3.4 and 5.4‐GHz). The physical layout is presented and explained the establishment of an LC equivalent circuit. Moreover, the second passband of the proposed dual‐band bandpass filter can be independently controlled by inserting the open‐circuited stubs at the end of the λ/2 bended resonators without increasing the circuit size. Simulation results show that the second passband can be ranged from 5.6 to 4.8‐GHz with the bandwidth of 400 ± 96‐MHz, whereas the first passband is fixed with the bandwidth of 280 ± 8.5‐MHz. The measured results exhibit the insertion losses (S21) lower than 1.2 and 1.4 dB, and the return losses (S11) of −23 and −32 dB at the first and second passbands, respectively, which show a good agreement with simulation results. The dual‐band microstrip filter is fabricated on RT/Rogers 4003 substrate with a compact size of 0.24λg × 0.25λg.
Design of A 2-3 GHz Down-Conversion Active Mixer With Improved Linearity
A down-conversion active mixer with high linearity and low noise behavior for 2-3 GHz wireless lo... more A down-conversion active mixer with high linearity and low noise behavior for 2-3 GHz wireless local area networks (WLAN) applications is presented. This mixer is designed based on the RF-TSMC $0.18\ \mu\mathrm{m}$ CMOS technology. In order to suppress third order nonlinearity, a new fully differential Darlington cell with a cross-connected topology is reported. As a result, the linearity of mixer is increased effectively. In addition, the proposed circuit employs an active load and current bleeding technique to increase the conversion gain (CG) and reduce the noise of the circuit in the frequency of interest. The simulated third-order input intercept point (IIP3) is 12.5 dB while conversion gain is 14.5 dB. The proposed circuit provides a low noise figure of 4.55 dB at 2.4 GHz. Its power consumption is 17.4 mW with power supply of 1.8V.
3.5-9 GHz Ultra-Wideband LNA With Variable Gain and Noise Cancellation for Wireless Communication
2020 10th Annual Computing and Communication Workshop and Conference (CCWC), 2020
In this paper, a noise-cancelling variable gain low noise amplifier (VG-LNA) is presented for ult... more In this paper, a noise-cancelling variable gain low noise amplifier (VG-LNA) is presented for ultra-wideband (UWB) applications. The proposed VG-LNA is designed for 3.5-9 GHz frequency bands using RF-TSMC CMOS $0.18\mu\mathrm{m}$ technology. The proposed LNA employs a common gate input stage and a common source second stage while a noise cancellation technique is used to minimize the noise figure of the input stage. By utilizing a feedback loop at the second stage, the gain of the LNA is continuously controlled. Simulation results exhibit the flat power gains (S21) of 12 dB, noise figure (NF) of 3.4 dB and input return loss (S11) less than −10 dB over the wide bandwidth of 3.5 to 9 GHz. The linearity parameter of third order input intercept point (IIP3) is −10.5 dBm at 8GHz. The proposed VG-LNA has power dissipation of 11.9 mW under a 1.3 V.
Micromachines, Aug 22, 2012
A distributed modeling approach has been developed to describe the dynamic behavior of ring reson... more A distributed modeling approach has been developed to describe the dynamic behavior of ring resonators. The model includes the effect of large amplitudes around primary resonance frequencies, material and electrostatic nonlinearities. Through a combination of geometric and material nonlinearities, closed-form expression for third-order nonlinearity in mechanical stiffness of bulk-mode ring resonators is obtained. Moreover, to avoid dynamic pull-in instability, the choices of the quality factor, ac-drive and DC-bias voltages of the ring resonators, with a given geometry are limited by a resonant pull-in condition. Using the perturbation technique and the method of harmonic balance, the expressions for describing the effect of nonlinearities on the resonance frequency and displacement are derived. The results are discussed in detail, showing the effect of varying operating conditions and the quality factor on the harmonic distortions and third-order intermodulation distortion. The detailed nonlinear modeling and distortion analysis are applied as appropriate tools to design bulk-mode ring resonators with low motional resistance and high linearity.
Design and Heuristic Optimization of a CMOS LNA for Ultra-Wideband Receivers
In this paper, an ultra-wideband (UWB) 3–10 GHz low noise amplifier (LNA) designed in a 0.18 μm R... more In this paper, an ultra-wideband (UWB) 3–10 GHz low noise amplifier (LNA) designed in a 0.18 μm RF-CMOS technology is presented. A noise cancelling technique has been used to improve the noise performance of the proposed UWB LNA. Moreover, the proposed LNA uses current reuse and inductive peaking techniques to provide low power dissipation and high flat power gain. An input impedance matching of 50 Ω is provided by a new network matching over the 3–10 GHz band. In addition, a new method for multiobjective optimization of the UWB-LNA using multi-objective inclined planes system optimization (MOIPO) is introduced. The proposed UWB-LNA has been simulated by Cadence Spectre-RF. The post-layout simulation results shows an input reflection coefficient (S11) below than −15 dB, flat power gain (S21) of 12.5 dB and noise figure (NF) of 3.8 dB over the whole bandwidth. The power consumption is about 5 mW at a 1.8 V power supply.
Analog Integrated Circuits and Signal Processing, Jun 24, 2019
This paper presents an active down-conversion mixer for wireless local area network applications.... more This paper presents an active down-conversion mixer for wireless local area network applications. The proposed downconversion mixer is designed for 2-3 GHz radio frequency (RF) band and an intermediate frequency of 100 MHz using RF-TSMC CMOS 0.18 lm technology. A new fully differential Darlington cell is introduced in the RF transconductance stage to effectively suppress third-order nonlinearity. In addition, the conversion gain and noise performance of the proposed mixer are improved by using an active load and current bleeding technique. The proposed mixer has been simulated by Cadence Spectre-RF. Post-layout simulation results show the third-order input intercept point can be improved up to 12.5 dBm by optimum biasing of the Darlington cell. The proposed mixer achieves the high conversion gain of 14.5 dB and the low double side-band noise figure of 4.55 dB at the input frequency of 2.4 GHz. The mixer operates at the supply voltage of 1.8 V with power consumption of 17.4 mW.
Advanced electromagnetics, Sep 4, 2018
In this paper, a new compact unit cell for a coplanar waveguide (CPW) lowpass filter (LPF) is pro... more In this paper, a new compact unit cell for a coplanar waveguide (CPW) lowpass filter (LPF) is proposed. By combining a pair of coupled parallel stepped impedance resonators (SIRs) and high impedance short stubs in the CPW line, a fifth-order elliptic lowpass filter unit cell (LUC) is designed. The extra transmission zero introduced by parallel coupled SIRs is used to extend the stopband and increase the roll-off rate. The characteristics of the proposed LUC is investigated to achieve a sharp roll-off and a wide stopband. The measured results are in accordance with the simulated results. It has an insertion loss less than 0.9 dB from dc to 6 GHz, and a wide-15 dB stopband from 7.5 to 18 GHz. In addition, the filter dimensions are as small as 4.9 mm × 8.7 mm, that is, 0.046λg 2 , where λg is the guided wavelength at the cutoff frequency. The filter structure is simple and easy to fabricate as well.
Modeling of Thermoelastic Damping in Bulk-Mode Vibrations of Micromechanical Ring Resonator Using Energy Method
In this paper, thermoelastic damping in bulk-mode vibrations of the micromechanical ring resonato... more In this paper, thermoelastic damping in bulk-mode vibrations of the micromechanical ring resonator is modeled using the energy method. Assuming that the thermoelastic coupling is very weak, the resonance frequencies and elastic displacements are first calculated using two-dimensional plane stress equations. An analytical expression for thermoelastic quality factor is then derived based on uncoupled linear thermoelasticity under adiabatic conditions. The validity of the derived expressions is demonstrated by comparing the analytical results with simulation results of modal and harmonic analysis using ANSYS software. Results show that the relative error of the analytical results decreases with increasing the ratio of the outer-to-inner ring radius. Moreover, the effects of resonance frequency and ring geometry on thermoelastic quality factor in various mode shapes of bulk-mode vibrations are discussed. The present analysis is applied as an appropriate tool to design bulk-mode ring resonators with high quality factor.
A Low Power Concurrent Dual-Band Low Noise Amplifier For WLAN Applications
A low power concurrent dual-band low noise amplifier (LNA) which can operate at the 2.4/5.2 GHz W... more A low power concurrent dual-band low noise amplifier (LNA) which can operate at the 2.4/5.2 GHz WLAN applications has been designed in RF-TSMC 0.18µm CMOS process technology. The proposed design provides a concurrent dual-band LNA with low power consumption, high gain and suitable noise figure and it can consume 2.49 mW with 1.5 V voltage supply. A common source stage with current-reused technique is used to create flat gain over wide bandwidth and reduce power consumption. By applying notch filters at input and output networks of the proposed LNA, the frequency response is shaped. The power gain (S21) of 15.1 dB, input return loss(S11) of –13.3 dB and noise figure (NF) of 2.7 dB are obtained at 2.4 GHz. At 5.2 GHz, it achieves a noise figure (NF) of 3.2 dB, a power gain (S21) of 13 dB and an input return loss (S11) of -12.4 dB.
A New Highly Power-Efficient Inverse Class-D PA for NB-IoT Applications
2020 10th Annual Computing and Communication Workshop and Conference (CCWC), 2020
The most power-consuming building blocks in Radio Frequency (RF) transceivers are power amplifier... more The most power-consuming building blocks in Radio Frequency (RF) transceivers are power amplifiers (PAs). This paper presents a fully integrated inverse class-D power amplifier with high efficiency for narrowband Internet of Things (NB-IoT) applications. In this design, two auxiliary PMOS transistors to mitigate the power dissipation are inserted to the class-D−1 PA. In addition, power efficiency has been improved by selecting a proper value for RF choke. An on-chip balun is designed to combine the output power, while its primary winding resonates with a capacitor at the fundamental frequency simultaneously. Operating from a 1-V supply and in frequency band of 1850–1910 MHz, the proposed PA can achieve a peak PAE of 63.74% and delivers 17.5 dBm output power to a $50\ \mathbf{\Omega}$ load. By using 180 nm TSMC RF technology, the proposed PA occupies a total chip area of 1.19 mm2, including pads.
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Papers by Abolfazl Bijari