Testing Methodology of Embedded DRAMs

Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.

2008 IEEE International Test Conference, 2008

In this paper, we investigate the retention time distribution of IBM's 65nm node embedded DRAM. We demonstrate that subthreshold current is the dominant leakage mechanism that determines data retention time, and the retention distribution can be attributed to array V t variation. Based on this study, we present a new technique for characterization of across-chip V t variation. The V t median value and standard deviation of transfer devices within an eDRAM array are estimated by analyzing the retention characteristics. The evaluation results are confirmed by the parametric test data. The proposed method is fast and can be used to monitor V t variation in both technology development and manufacture. The impact of array V t spread on the retention and performance of eDRAM is discussed.

IEEE Transactions on Computers, 2002

AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012

Dynamic supply current test method (I DDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the I DDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of I DDT test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

2021

In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.

The minimum feature size of dynamic RAM has been down - scaled, so several studies have been carried out to determine ways to protect cell data from leakage current in many areas. Due to leakage sources, permanent error occurs. Many permanent faults are a result of manufacturing defects, which can be detected during manufacture testing. These errors can also occur at runtime. A self - contained adaptive system for detecting and bypassing permanent errors in on - chip interconnects is proposed. This system reroutes data on erroneous links to a set of spare wires without interrupting the data flow

VDAT 2004, 2004

This paper reviews algorithms for memory testing. Various fault models like stuck-at faults, coupling faults, transition faults have been included. March algorithms for testing memories and their fault coverage are compared. Our contribution is towards a SRAM fault model being described at HDL. We further propose to evaluate algorithms using appropriate fault signatures alongwith the proposed model. ©

Proceedings of the …, 2000

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is ...

Fast development of memory devices cause more area occupation of memory in a chip and the strong market competition have increased the standards of the produced memories. The increased demand on reliability has, in turn, stressed the importance of failure analysis and device testing techniques. More and more effort and thought is being dedicated to the study of testing memory devices with regards to new fault models, fault diagnosis and new memory architectures. In order to detect these faults, March test has been widely used. However, some defects on SRAM cells may not be detected by the conventional March tests. This detection of defects in CMOS SRAM has been a time consuming process. Hence we go for current testing method. This paper implements a transient current testing (I DDT ) method to detect defects in CMOS SRAM cells. By monitoring a transient current pulse during a transition write operation or a read operation, defects can be detected. In order to measure the transient current pulse, a current monitoring circuit is designed.

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014

Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it's still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition.