In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
IEEE Transactions on Very Large Scale Integration Systems, 2016
This brief proposes an on-line transparent test technique for detection of latent hard faults whi... more This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in first-input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.
A Distributed BIST Scheme for NoC-Based Memory Cores
ABSTRACT This paper proposes a distributed Memory Built- In-Self Test (MBIST) architecture employ... more ABSTRACT This paper proposes a distributed Memory Built- In-Self Test (MBIST) architecture employing a hybrid technique for testing heterogeneous memory cores interconnected using NoC. In the proposed architecture, the memory cores are placed in different groups based on distance and timing constraints. Each group has a dedicated BIST controller which performs parallel March test on all the cores in a group while the groups are tested in a pipeline. The paper also proposes a test schedule for the proposed architecture to keep the test power within the power budget. Experiments performed on ITC'02 benchmark circuit confirms that our proposed test schedule performs a more power constrained test as compared to dedicated BIST technique. Moreover, experimental results indicate real estate benefits for the proposed distributed BIST architecture in comparison to other reported techniques.
Classification and Workload Balancing of Multi-threaded Application on Embedded Platforms
As embedded devices start supporting computationally intensive multi-threaded applications, they ... more As embedded devices start supporting computationally intensive multi-threaded applications, they tend to become power hungry and dissipate more heat. As a result, the reliability and performance of these devices take a hit. In this paper we propose a software based thermal management technique for embedded systems executing multi-threaded applications. The proposal involves a two pronged approach of thread classification and workload balancing of processing cores. The proposed thermal management technique when experimented on ODROID-XU4 ARM based embedded platform with PARSEC 3.0 application benchmark suite shows 6 o C reduction in average temperature of the embedded platform while 3.2 times increase in its performance compared to other state-of-art approaches.
ABSTRACT This paper proposes a Built-In-Self test technique that utilizes refresh circuit to perf... more ABSTRACT This paper proposes a Built-In-Self test technique that utilizes refresh circuit to perform functional tests on DRAMs. The refresh re-use technique overcomes the requirement of additional Design-For-Testability hardware as tests are performed via the on-chip refresh circuit. Moreover, to perform test read followed by test write operations on a DRAM, each read operation gets completed within the refresh operation of the DRAM itself, avoiding separate test read cycles. As a result, the entire time between two refresh cycles is allowed for write operation. The increase in write cycle time is utilized in performing power aware test of a number of DRAM cores embedded in SoCs. Analytic predictions indicate that the refresh re-use technique when applied for testing a number of DRAMs, allows parallel write operation on a larger number of DRAMs within a given test power budget as compared to normal BIST approaches. Experimental results for the BIST architecture proposed in the paper indicate real estate benefits in comparison to other reported techniques.
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip
Lecture Notes in Computer Science, 2012
ABSTRACT Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solu... more ABSTRACT Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solution for testing embedded memory cores in Systems-On-Chip. The reuse of the available on-chip network to act as Test Access Mechnism brings down the area overhead as well as reduces test power. However, reducing the time to test still remains a problem due to latency in transporting the test instruction from BIST circuit to the memory cores. We have proposed a NoC based test architecture where a number of BIST controllers are shared by memory cores. A Particle Swarm Optimization (PSO) based technique is used (i) to place the BIST controllers at fixed locations and (ii) to form clusters of memories sharing the BIST controllers. This reduces the test instruction transport latency which in turn reduces the total test time of memory cores. Experimental results on different sizes of mesh based NoC confirm the effectiveness of our PSO based approach over heuristic techniques reported in literature as well as used in the industry.
In this paper, a transparent test technique for testing permanent faults developed during field o... more In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Reusing the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead. Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.
In this paper, we present to the embedded research community an Embedded Platform as a Service fa... more In this paper, we present to the embedded research community an Embedded Platform as a Service facility named SLePaaS that allows researchers remote access to experimental hardware and a collection of online tools that would facilitate research on thermal management of embedded systems. SLePaaS serves a dual purpose-provides access to actual hardware for experiments on one hand and reduces experimental cost and time on the other. With this facility, researchers neither have to rely on simulation models nor purchase or customize any experimental platform for a specific problem. In addition, the platform provides tool support, specifically for researchers working in problems related to thermal management. Presently, three tools are provided by the SLePaaS platform. The first tool helps users obtain performance, power and thermal profile of applications running on different hardware platforms. The second is a thermal value predictor tool that aids task schedulers in allocating tasks to processors based on the thermal profile of applications. The third tool is a platform predictor that helps users to decide the best platform to run an OpenCL application given a target optimization objective. All the tools have been validated for their performance and accuracy against standard benchmark applications. A prototype implementation of SLePaaS along with the three tools is available for use. INDEX TERMS Embedded system, thermal management, task scheduling, embedded platform, heterogeneous processor, OpenCL, RMI.
Classification and Workload Balancing of Multi-threaded Application on Embedded Platforms
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020
As embedded devices start supporting computationally intensive multi-threaded applications, they ... more As embedded devices start supporting computationally intensive multi-threaded applications, they tend to become power hungry and dissipate more heat. As a result, the reliability and performance of these devices take a hit. In this paper we propose a software based thermal management technique for embedded systems executing multi-threaded applications. The proposal involves a two pronged approach of thread classification and workload balancing of processing cores. The proposed thermal management technique when experimented on ODROID-XU4 ARM based embedded platform with PARSEC 3.0 application benchmark suite shows 6 o C reduction in average temperature of the embedded platform while 3.2 times increase in its performance compared to other state-of-art approaches.
Automatic Extraction of Structural Model from Semi Structured Software Requirement Specification
2018 IEEE/ACIS 17th International Conference on Computer and Information Science (ICIS)
The software requirement specifications are usually documented either in unstructured, semi struc... more The software requirement specifications are usually documented either in unstructured, semi structured or structured format. The requirements specified in unstructured format are written in simple continuous paragraph and the structured format specifies requirements by means of diagrams. The semi-structured format represents requirements with the help of some keywords. Literature suggests that the rule based work has been the common choice for unstructured format of documenting. However, these rule based works do not yield satisfactory results for semi-structured format. Consequently, these rules need to re-framed in order to apply them for the semi-structured formatted documents. In this paper, we present an improvement on the existing rules considering the keywords present in the text. The technique involves automatic extraction of the class diagrams using NLP tools and techniques. Along with existing rules, the newly formulated rules have been tested for different case studies and suitable metrics have been devised to evaluate the obtained results. Results show that the automatically generated class diagram have 82% average precision value and 94% average recall value when compared to the class diagrams generated by the human experts.
Traditional citation networks which form the basis of study of community interaction tend to leav... more Traditional citation networks which form the basis of study of community interaction tend to leave out a lot of articles which are related to a community but have not been directly cited by the members of it. As a result, the parameters estimated during the study of community interaction remain fairly inaccurate. In this work, we tend to perform a more accurate community interaction study by proposing a context-aware citation network which allows inclusion of papers to a community which have both direct as well as indirect relevance to the existing members of the community. A comparative analysis of computer science community networks built upon the proposed citation network and traditional citation network using the CiteSeer dataset show about 20-30% better results in favour of the former.
Classification and Workload Balancing of Multi-threaded Application on Embedded Platforms
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020
As embedded devices start supporting computationally intensive multi-threaded applications, they ... more As embedded devices start supporting computationally intensive multi-threaded applications, they tend to become power hungry and dissipate more heat. As a result, the reliability and performance of these devices take a hit. In this paper we propose a software based thermal management technique for embedded systems executing multi-threaded applications. The proposal involves a two pronged approach of thread classification and workload balancing of processing cores. The proposed thermal management technique when experimented on ODROID-XU4 ARM based embedded platform with PARSEC 3.0 application benchmark suite shows 6 o C reduction in average temperature of the embedded platform while 3.2 times increase in its performance compared to other state-of-art approaches.
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Papers by Bibhas Ghoshal