The State-of-Art and Future Trends in Testing Embedded Memories

IEE Proceedings - Computers and Digital Techniques, 2006

The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different stress combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the fault coverage (FC) of the test algorithms, that the highest FC is obtained at a low voltage level and that the highest detected number of unique faults is obtained at a high voltage level. They also show that the tests with the most promising FC, based on the theory, also tend to have the highest FC in practice. Moreover, the test results show that some algorithms detect faults that cannot be explained with the existing fault models, indicating that the existing fault models still leave much to be explained; for example, no theoretical basis exists to model the stresses and the predicted FC for a given test.

Today's submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements. Embedded RAMs are those whose address, data, and read/write controls cannot be directly controlled or observed through the chip's 1/0 pins. Testing these memories, which are incorporated on a large percentage of VLSI devices are harder just because of the lack of controllability of its inputs and observe ability of its outputs. Testing such RAMs is the main objective of this paper. It is challenging to test embedded RAMs, and hence we will discuss techniques-design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs.

2010 International Conference on Signal Acquisition and Processing, 2010

As embedded memory area on-chip is increasing and memory density is growing, problem of faults is growing exponentially. Considering the increasing impact that memory yield has on SoC yield in today's memory dominant SoCs, a high memory yield is required for acceptable levels of SoC yield. Thus memory fault modeling, detection and repair has come to take an important place. The architecture presented in this work implements the newly defined March SS algorithm which helps in detecting some recently modeled faults. Also, a word-oriented memory Built-in Self Repair methodology, which supports on-the-fly memory repair, is employed to repair the faulty locations indicated by the MBIST controller presented.

IEEE Transactions on Industrial Electronics, 2000

2012 IEEE Students' Conference on Electrical, Electronics and Computer Science, 2012

In modern day, embedded memory density and area on-chip is increasing, it is essential to define new test algorithms which fulfill the need of detecting new faults. The existing March algorithms consist of as many as four or seven operations per March element. In this paper we have presented an optimization of architecture which can implement these new March BLC tests having number of operations per element according to the today's growing needs of embedded memory testing with enhanced fault using Verilog HDL as a primary language and used Modelsim SE 6.5 f as simulation tool.

2012

Abstract—Memories are one of the most universal cores. On average embedded RAMs occupy 90 % area in system-on-chip (SOC), so embedded memory test design has become an essential part of the SOC development infrastructure. Here we designed reusable memory built in self test (MBIST) engine for memory test, which also gives useful information for fault diagnosis. A simple architecture for built in self repair is implemented. Integrating BISR in MBIST improves the chip yield. SOC consists of many memory models. Like, SRAM, FLASH, ROM etc, we consider here only SRAM type of memory core.Here we will see what the functional model of SRAM is and what types of Functional Faults, Fault Models and Defects exist in SRAM cores due to process variation and manufacturing. xilinx spartan3E tool used for synthesise and simulation.

2007

With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing Bitmap Diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete Bitmap to the tester. The proposed methodology supports testing through a very low cost ATE. This architecture is partitioned to achieve sharing among various memories and atspeed testing.

Journal of Electronic Testing, 1992

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit, the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5'~, if the RAM is organized into an nxl array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a 1M-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.

12th IEEE European Test Symposium (ETS'07), 2007

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple search strategies or restrict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.

The International Technology Roadmap for Semiconductors predicts memories to occupy more than 90% of the chip silicon area in the foreseeable future. Due to their ultra large scale of integration and vastly complex structures, memory arrays are far more vulnerable to defects than the remaining parts of integrated circuits. Embedded memories have already started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in test procedures. Many types of failures, often not seen earlier, originate in the highest density areas of semiconductor devices where diffusions, polysilicon, metallization, and fabricated structures are in extremely tight proximity to each other. Failing to properly test all architectural features of the embedded memories can eventually deteriorate the quality of test, and ultimately hinder yield.