Shi-Yu Huang

National Tsing Hua University, Electrical Engineering, Faculty Member

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Shi-Yu Huang received his B.S. and M.S. degrees in Electrical Engineering from National Taiwan University in 1988, and 1992, and a Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. He has been on the faculty of the EE Dept., National Tsing Hua University, Taiwan, since 1999. His research interests include VLSI design, automation, and testing, with a current emphasis on All-Digital Phase-Locked Loop (ADPLL) design and its application in parametric fault testing and monitoring in 3D ICs. He ever served as Program Co-Chair or General Chairs or Co-Chairs in several IEEE conferences/symposia/workshops (2004, 2009 ATS, 2005, 2006 MTDT, 2014, 2015 VLSI-DAT, and 2017 ITC-Asia). He ever served as an Associate Editor for IEEE Trans. on Computers from 2015 to 2018.

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Logarithmic CMOS image sensor through multi-resolution analog-to-digital conversion

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

In this paper we present a CMOS image sensor design with a better sensitivity to low light intens... more In this paper we present a CMOS image sensor design with a better sensitivity to low light intensity. This feature is achieved through a multi-resolution analog-to-digital converter (ADC). By doing so, the opto-electrical characteristic of a sensor cell can be finely tuned. A costeffective architecture for realizing the required ADC is also proposed. This architecture leads to a faster conversion time as well as a smaller area. A simulation environment with post-layout accuracy is incorporated to demonstrate the advantages. It shows that a number of images can be captured more clearly than a traditional sensor.

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A novel methodology for transistor-level power estimation

International Symposium on Low Power Electronics and Design, Aug 12, 1996

Transistor-level power simulators, which are more accurate than logic-level power estimators, hav... more Transistor-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In this paper, we introduce a method which extends the Monte-Carlo approach for deriving the average power dissipation of a circuit using transistor-level power simulators. To reduce the simulation time, we propose a mixedlevel extrapolation technique to speed up the convergence rate of the process, and thereby to achieve a good balance between simulation time and accuracy. Experimental results show that this is a promising method for deriving the accurate power dissipation of a circuit within reasonable time budget.

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Monitoring the delay of long interconnects via distributed TDC

Interconnects are sophisticated in a multi-die IC using integration technology such as interposer... more Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this paper by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Oct 1, 2020

We propose a new deterministic approach for remote sensing retrieval, called modified total least... more We propose a new deterministic approach for remote sensing retrieval, called modified total least squares (MTLS), built upon the total least squares (TLS) technique. MTLS implicitly determines the optimal regularization strength to be applied to the normal equation first-order Newtonian retrieval using all of the noise terms embedded in the residual vector. The TLS technique does not include any constraint to prevent noise enhancement in the state space parameters from the existing noise in measurement space for an inversion with an ill-conditioned Jacobian. To stabilize the noise propagation into parameter space, we introduce an additional empirically derived regularization proportional to the logarithm of the condition number of the Jacobian and inversely proportional to the L2-norm of the residual vector. The derivation, operational advantages and use of the MTLS method are demonstrated by retrieving sea surface temperature from GOES-13 satellite measurements. An analytic equation is derived for the total retrieval error, and is shown to agree well with the observed error. This can also serve as a quality indicator for pixel-level retrievals. We also introduce additional tests from the MTLS solutions to identify contaminated pixels due to residual clouds, error in the water vapor profile and aerosols. Comparison of the performances of our new and other methods, namely, optimal estimation and regression-based retrieval, is performed to understand the relative prospects and problems associated with these methods. This was done using operational match-ups for 42 months of data, and demonstrates a relatively superior temporally consistent performance of the MTLS technique. Index Terms-Condition number of matrix, ill-conditioned inverse methods, regularization, satellite remote sensing, sea surface temperature (SST), total error, total least squares (TLS). I. INTRODUCTION P ARAMETER estimation from remotely sensed satellite measurements can be broadly categorized into two groups: a) the direct method, which directly correlates the measure

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Modeling and analysis of power in multicore network processors

2008 IEEE International Symposium on Parallel and Distributed Processing, 2008

With the emergence of multicore network processors in support of high-performance computing and n... more With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing significance. Lower-power multicore processors, such as the Intel IXP network processors, have been employed in network devices to try to address this problem; however, effective tools are still needed to assist in the exploration of the "performance versus power" design space. In this paper, we present a composite power model that simultaneously leverages three existing power-modeling tools (Cacti, Wattch, and Orion) to model the power consumption of Intel IXP2400. This model is then integrated with an open-source Intel IXP2400 NP simulator called NePSim2 and validated against its datasheet to within 5% of actual power consumption. We utilize the simulator and power model to explore how architectural parameters affect the performance and power consumption of a set of highperformance security applications, thus delivering valuable insights to chip architects for designing energy-efficient multicore network processors.

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Versatile Transition-Time Monitoring for Interconnects via Distributed TDC

IEEE design & test, Dec 1, 2016

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Circuit and Methodology for Testing Small Delay Faults in the Clock Network

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Oct 1, 2018

A clock network is not only difficult to design, but also challenging to test. For high-performan... more A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a "special test clock signal", which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

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Online slack-time binning for IO-registered die-to-die interconnects

2016 IEEE International Test Conference (ITC), 2016

In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible ... more In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS pro...

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks

Proceedings of the 24th Asia and South Pacific Design Automation Conference

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artific... more Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

IEEE Design & Test, 2016

Detection of delay faults in 3-D interconnects is crucial for building reliable 3-D ICs. This pap... more Detection of delay faults in 3-D interconnects is crucial for building reliable 3-D ICs. This paper presents a test methodology based on a globalring structure with a variable output thresholding technique to detect delay faults in multipin 3-D interconnects in multidie 3-D ICs. The proposed test architecture with an enhanced clock period measurement circuit detects delay faults in multipin 3-D interconnects with an accuracy of 10 ps.

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On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs

2014 IEEE 23rd Asian Test Symposium, 2014

Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro... more Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro-migration effects that could lead to unexpected resistance increase after certain time of field operation. To cope with this reliability threat, we present an on-line monitoring method that aims to continuously detect excessive transition time occurring to a TSV (which often indicates performance degradation). Our method attaches a monitor to the termination end of a TSV. Any transition there is converted into a pulse-width, which is further compared to a dynamically tunable threshold. A Timing Failure Threat (TFT) is thereby detected when the pulse-width exceeds the threshold. This method can be applied to a large number of TSVs easily since the monitoring results are binary and can be stored in FFs forming a scan chain for easy access.

On speeding up extended finite state machines using catalyst circuitry

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001

We propose a timing optimization technique for a complex finite state machine that consists of no... more We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block-which includes a piece of combinational logic and several other registers-to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit's functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial applicationa Built-In Self-Test (BIST) circuit for static random access memories (SRAMs). The synthesis result indicates a 47% clock cycle time reduction.

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Testing of small delay faults in a clock network

2016 21th IEEE European Test Symposium (ETS), 2016

A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For hig... more A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel test method to determine if a clock network has any small delay faults. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 50ps through outlier analysis, while locating the FFs affected by the fault.

A wide-range clock signal generation scheme for speed grading of a logic core

2016 International Conference on High Performance Computing & Simulation (HPCS), 2016

In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessa... more In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessary in order to ensure an adequate operating margin for accommodating all kinds of variation (e.g., PVT variation), and to guide the dynamic VDD tuning process as well. In general, a speed grading method for a logic core can be performed by repeating a specific delay test session, (e.g., built-in self-test with the latch-off capture scheme), with varying test clock frequencies to derive the maximum operating speed of a specific core under testing. In this paper, we propose an easy-to-use speed grading method featuring a wide-range synthesizable clock generation scheme so that it can support a logic core that could be used with different supply voltages and speeds in different application domains.

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009

In this paper, we propose a transitive closure graph-based representation for general floorplans,... more In this paper, we propose a transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.

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Oscillation-Based Prebond TSV Test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013

ABSTRACT Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-G... more ABSTRACT Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)

IEEE Journal of Solid-State Circuits, 2009

BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read o... more BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read operation in an SRAM design without sacrificing any circuit performance at all. This scheme has very low area overhead since it uses commonly existing memory BIST circuit for tracking the worst-case silicon speed of the bitlines. It is also highly scalable and therefore suitable for an SRAM compiler that needs to support a wide range of different configurations. Measurement results of 8 manufactured chips of a 2 K-bit SRAM design using TSMC 0.18-m CMOS technology demonstrate that it can indeed rescue one originally failing chip, while still warranting correct functionality of all the other seven chips, even under some injected variations in which conventional schemes may fail badly.

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Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked inte... more This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire. Index Terms-2.5-D stacked integrated circuit (IC), delay characterization, delay testing, interposer wire, post-bond IC, resistive bridging fault.

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Feedback-Bus Oscillation Ring: A General Architecture for Delay Characterization and Test of Interconnects

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015

In this paper we propose a flexible delay characterization and test architecture, called Feedback... more In this paper we propose a flexible delay characterization and test architecture, called Feedback-Bus Oscillation Ring (FB-OR), for die-to-die interconnects in a 3D IC. As compared to previous works, it is unique in its ability to streamline the characterization/test operations for a set of arbitrary interconnects with multiple pins sprawling multiple dies. During the Design-for-Testability stage, one common feedback-bus (connected to all dies in the IC under characterization/test) is inserted. Through this feedback-bus, an oscillation ring can be formed dynamically and the Variable-Output-Threshold (VOT) technique can be applied to characterize the delay of one interconnect segment at a time. Experimental results indicate that this method is not only flexible and scalable, but requiring only a small area overhead.

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Speeding up the Byzantine fault diagnosis using symbolic simulation

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

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