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Design for C-Testability
Reliability and Hardware Overhead Analysis
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Electronic, Optical and Magnetic Materials

Easily testable and fault-tolerant FFT butterfly networks

Profile image of Jin-Fu LiJin-Fu Li

2000, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

https://doi.org/10.1109/82.868460
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11 pages

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Abstract

With the advent of deep submicron very large scale integration technology, the integration of a large fast-Fourier-transform (FFT) network into a single chip is becoming possible. However, a practical FFT chip is normally very big, so effective testing and fault-tolerance techniques usually are required. In this paper, we first propose a C-testable FFT network design. Only 20 test patterns are required to cover all combinational single-cell faults and interconnect stuck-at and break faults for the FFT network, regardless of its size. A spare-row based fault-tolerant FFT network design is subsequently proposed. Compared with previous works, our approach shows higher reliability and lower hardware overhead, and only three bit-level cell types are needed for repairing a faulty row in the multiply-subtract-add module. Also, special cell design is not required to implement the reconfiguration scheme. The hardware overhead for the testable design is low-about 4% for 16-bit numbers, regardless of the FFT network size.

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