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Key research themes
1. What are the advances and challenges in process technologies enabling scaling and integration of very large scale integrated circuits?
This research theme focuses on innovations and obstacles in the semiconductor process technologies necessary for continued device scaling, improved performance, and 3D integration in VLSI. Understanding these technology enablers and their trade-offs is critical for sustaining Moore's law and enabling next-generation comparable cost, power, and speed improvements in VLSI devices.
Key finding: This paper analyzes emerging thin film deposition, etch, and patterning advancements—such as self-aligned multi-patterning and extreme ultraviolet (EUV) lithography—that are crucial to enabling vertical (3D) scaling in... Read more
Key finding: Introduces a novel fabrication approach using reticle stitching to interconnect 16 deep UV reticles into an extremely large-area (7744 mm²) active superconducting IC (ELASIC), demonstrating scalable monolithic 3D active chip... Read more
Key finding: This study shows that scaling ETSOI MOSFET channel thickness down to 3.5 nm significantly improves short-channel control (e.g., drain-induced barrier lowering reduced to 100 mV at 18 nm gate length) without performance... Read more
Key finding: Demonstrates that SiGe channel pMOSFETs intrinsically reduce Negative Bias Temperature Instability (NBTI) degradation due to an energy decoupling mechanism between SiGe channels and gate dielectric defects, which also lowers... Read more
2. How can architectural and design methodologies address interconnect challenges in gigascale VLSI integration?
This theme examines system-level and design-flow solutions to mitigate wiring delay, crosstalk, routing congestion, and variability arising from ever-increasing interconnect complexity with nanoscale and gigascale VLSI chips. It focuses on novel architectural regularity, timing-aware physical synthesis, and hierarchical or 3D design flows that anticipate and optimize for interconnect parasitics.
Key finding: Highlights that in deep submicron VLSI, interconnect capacitance and coupling dominate delay and timing uncertainty, making traditional top-down synthesis inadequate. Proposes design methodologies integrating wire... Read more
Key finding: Proposes a novel CORDIC algorithm optimizing micro-rotation sequences using Taylor series expansions and high-speed MSB detection, eliminating complex scaling factor compensation. The architecture flexibly balances accuracy,... Read more
Key finding: Presents a data-dependence driven logic reformulation that eliminates redundant operations in conventional and binary-to-excess-1 converter-based carry select adders (CSLA). The optimized CSLA design achieves ~32-35%... Read more
Key finding: Designs and validates a low-swing differential conditional capture flip-flop optimized for LC resonant clock distribution networks, reducing clock power by 6.5% with 19% area overhead. It characterizes frequency-dependent... Read more
3. What advancements in integrated circuit design automation and physical design enable monolithic 3D integration and support giga-scale system-on-chip designs?
This area addresses novel design flows, CAD methodologies, and testing approaches developed to handle increased integration density, heterogeneous 3D stacking, and complexity in giga-scale SoCs. It emphasizes the interplay of design, verification, testability, and manufacturability constraints in modern monolithic 3D integrated circuits and large SoCs.
Key finding: Presents a practical, commercial-grade netlist-to-layout design flow that enables gate-level monolithic 3D IC design by flattening 3D placement constraints into 2D tools, followed by post-processing to assign tiers and insert... Read more
Key finding: Identifies the critical need to extend Built-In Self-Test (BIST) capabilities beyond memories to logic to handle increasing complexity in deep submicron ICs, where conventional external testing and scan approaches become... Read more
Key finding: Analyzes the growing gap between device integration capacity and design productivity in giga-scale SoC design, highlighting physical design challenges such as interconnect delay, power consumption, timing closure, and... Read more
Key finding: Demonstrates the use of high-resolution focused ion beam (FIB) milling as a flexible post-fabrication technique for circuit restructuring, enabling nanoscale precision cuts and conductive joins between multilayer... Read more