On the design of an on-line FFT network for FPGA's

Increased demand and advancements in product design in the field of communication, multimedia, security and safety equipment and other industrial and scientific products have created the need for high volume, low cost, multifunction, DSP based frequency analyzers that can use Fast Fourier Transform ( FFTs )for their signal processing or data manipulation. The paper deals with implementation of FFT algorithms that can compute fourier transform of varied signals in real time for frequency analysis of signals on FPGAs (Spartan-6). With large demand for high dynamic range for applications, floating point implementation is used as fixed point implementation becomes increasingly expensive. The inherent massive parallelism of FPGAs allows these solutions to be competitive to software equivalent.

Electronics, 2018

The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas...

2009

signal processing and communications systems. The performance of the FFT component is a key factor in evaluating the overall system performance, and it is common to use it as a benchmark for the whole system. Many attempts have been made to enhance the FFT performance, both on algorithm and implementation levels. Software and hardware designs exist to implement this component. In this paper, an optimized hardware implementation of FFT processor on FPGA is presented, where the steps of Radix-2 FFT algorithm are well analyzed and an optimized design is developed as a result, with full exploitation of the hardware platform capabilities to achieve optimum performance. The performance results of the proposed design are demonstrated, and compared to other related works and reference designs.

2007

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to choose the algorithm and architecture to implement it. This paper explains the realization of a Split Radix FFT (SRFFT) processor based on a pipeline architecture reported before by the same authors. This architecture has as basic building blocks a Complex Butterfly and a Delay Commutator. The main advantages of this architecture are:

Procedia Computer Science, 2016

The need of complex multipliers in mathematics seems to be a very important aspect. The application used as a complex operation with respect to the real and imaginary numbers together. In many of the practical aspect the design substantiated to be a aiding hand for co-functionality units. Since to carry out the operations more correctly so as to elluct the technical peccadilloes. The results show that proposed FFT consumes very less resources in terms of slices, flip flops and multipliers to provide cost effective solution for DSP applications The proposed design has a desideratum for high efficacy eliciting structure in terms of accuracy. The device used in this proposed design is 7a30tcsg324-3.

2008 IEEE International Conference on Computer Design, 2008

The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024point FFT with 2 processing elements using 45nm process technology, including area, timing, power and place-and-route results.

AL-Rafdain Engineering Journal (AREJ)

This paper develops a system level architecture for implementing a cost-efficient, FPGA-based reconfigurable two dimensional (2D) FFT system. The adopted approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two extremes are optimized based on using run time reconfiguration, double buffering technique, shared Dual Ported RAM (DPRAM) modules and the "hardware virtualization" to reuse the available processing components. The system employs two one Dimensional (1D) FFT processor each with sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT engine. Thus the architecture supports transform length of 256X256 complex points, as a demonstrator to the design idea, using fixed-point arithmetic and has been developed using radix-4 butterfly architecture. The simulation results that have been performed using VHDL modeling language and ModelSim software shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices.

2019

Many “Digital Signal Processing” applications uses “fast fourier transform”. Common practice is to run FFT on Digital signal processor or Application specific IC. In this paper 8 point FFT is implemented using Radix 2 butterfly method. 3 stage pipelining is used to speed up the processing. Complex multiplication is done by incorporating complex Vedic multiplier which further enhances the speed.

2013

Abstract—In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log 4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/area. I.

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

High performance VLSI-based FFT architectures are key to signal processing and telecommunication systems since they meet the hard real-time constraints at low silicon area and low power compared to CPU-based solutions. In order to meet these goals, this paper presents a novel VLSI FFT architecture based on combining three consecutive radix-4 stages to result in a 64-point FFT engine. Cascading these 64-point FFT engines consequences an improved architecture design featuring certain characteristics. First, it can efficiently accommodate large input data sets in real time. It also simplifies processing requirements due to the radix-4 calculations. Finally, it reduces memory requirements and latency to one third compared to the fully unfolded radix-4 architecture. Two different implementations are utilized in order to validate the architecture efficiency: a FPGA implementation of a 4096-point FFT achieving a throughput of 4096 point/20.48 usec, and a VLSI implementation sustaining a throughput of 4096 point/3.89 usec.